Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

REV32

Test 1: uops

Code:

  rev32 x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000

Test 2: Latency 1->2

Code:

  rev32 x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	259434	10107	10214	10214	10001	10100
10204	10030	10101	10101	10107	259311	10107	10214	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	259528	10030	10038	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10080	10042	10042	10064	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	10020	10011	10010

Test 3: throughput

Count: 8

Code:

  rev32 x0, x8
  rev32 x1, x8
  rev32 x2, x8
  rev32 x3, x8
  rev32 x4, x8
  rev32 x5, x8
  rev32 x6, x8
  rev32 x7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	26908	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26740	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	0	80015	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	28002	80038	80038	80043	266812	80042	80044	80020	80011	80010
80024	26782	80021	80021	80020	277404	80020	80020	80098	80067	80010
80024	26761	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26717	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26717	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26717	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26717	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26717	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26717	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26717	80021	80021	80020	277404	80020	80020	80020	80011	80010