Icestorm: CMN (register, 32-bit) measurements

Code:

  cmn w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	503	1001	1001	1000	3000	1000	1000	2000	1001
1004	403	1001	1001	1000	3000	1000	1000	2000	1001
1004	399	1001	1001	1000	3000	1000	1000	2000	1001
1004	402	1001	1001	1000	3000	1000	1000	2000	1001
1004	397	1001	1001	1000	3000	1000	1000	2000	1001
1004	397	1001	1001	1000	3000	1000	1000	2000	1001
1004	397	1001	1001	1000	3000	1000	1000	2000	1001
1004	397	1001	1001	1000	3000	1000	1000	2000	1001
1004	397	1001	1001	1000	3000	1000	1000	2000	1001
1004	402	1001	1001	1000	3000	1000	1000	2000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn w0, w1
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519464	20110	20218	30221	20001	10100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519638	20018	20036	30041	20001	10010
20024	20030	20011	20011	20018	519638	20018	20036	30044	20001	10010
20024	20030	20011	20011	20018	519638	20018	20036	30044	20001	10010
20024	20030	20011	20011	20018	519638	20018	20036	30044	20001	10010
20024	20030	20011	20011	20018	519638	20018	20036	30044	20001	10010
20024	20030	20011	20011	20018	519638	20018	20036	30110	20015	10010
20024	20030	20011	20011	20018	519638	20018	20036	30044	20001	10010
20024	20030	20011	20011	20018	519638	20018	20036	30044	20001	10010
20024	20030	20011	20011	20018	519638	20018	20036	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn w0, w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519327	20107	20214	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519516	20018	20034	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 4: throughput

Count: 8

Code:

  cmn w0, w1
  cmn w0, w1
  cmn w0, w1
  cmn w0, w1
  cmn w0, w1
  cmn w0, w1
  cmn w0, w1
  cmn w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29112	80114	80114	80118	240351	80117	80218	160242	80014	100
80204	29019	80114	80114	80119	240351	80117	80217	160240	80015	100
80204	29082	80115	80115	80119	240360	80120	80220	160234	80013	100
80204	29004	80113	80113	80118	240351	80117	80220	160240	80013	100
80204	29056	80113	80113	80118	240360	80120	80220	160240	80013	100
80204	29092	80113	80113	80118	240354	80118	80220	160240	80015	100
80204	29118	80115	80115	80119	240357	80119	80220	160240	80013	100
80204	29052	80115	80115	80119	240351	80117	80220	160312	80052	100
80204	29077	80113	80113	80118	240354	80118	80220	160240	80013	100
80204	29092	80113	80113	80118	240354	80118	80220	160240	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	29983	80035	80035	80039	240166	80040	80041	160062	80026	10
80024	29090	80034	80034	80039	240159	80039	80041	160020	80011	10
80024	28891	80021	80021	80020	240112	80020	80020	160020	80011	10
80024	28980	80021	80021	80020	240101	80020	80020	160020	80011	10
80024	29050	80021	80021	80020	240103	80020	80020	160020	80011	10
80024	29117	80021	80021	80020	240110	80020	80020	160020	80011	10
80024	28937	80021	80021	80020	240112	80020	80020	160020	80011	10
80024	28984	80021	80021	80020	240095	80020	80020	160020	80011	10
80024	29049	80021	80021	80020	240103	80020	80020	160020	80011	10
80024	29100	80021	80021	80020	240114	80020	80020	160020	80011	10

CMN (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations