Icestorm: MRS (CNTFRQ_EL0) measurements

Code:

  mrs x0, cntfrq_el0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	? int output thing (e9)	? int retires (ef)
1004	16039	1001	1001	1001	1000
1004	16040	1001	1001	1001	1000
1004	16038	1001	1001	1001	1000
1004	16040	1001	1001	1001	1000
1004	16040	1001	1001	1001	1000
1005	16325	1017	1017	1001	1000
1004	16041	1001	1001	1001	1000
1004	16040	1001	1001	1001	1000
1004	16038	1001	1001	1001	1000
1004	16039	1001	1001	1001	1000

Count: 8

Code:

  mrs x0, cntfrq_el0
  mrs x1, cntfrq_el0
  mrs x2, cntfrq_el0
  mrs x3, cntfrq_el0
  mrs x4, cntfrq_el0
  mrs x5, cntfrq_el0
  mrs x6, cntfrq_el0
  mrs x7, cntfrq_el0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 16.0053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	1280080	80101	80101	0	100	300	100	200	200	0	0	80018	0	0	80100
80204	1280083	80101	80101	0	100	300	100	200	200	0	0	80034	0	0	80100
80204	1280080	80101	80101	0	100	300	100	200	200	0	0	80001	0	0	80100
80205	1280441	80120	80120	0	100	300	100	200	200	0	0	80001	0	0	80100
80205	1280436	80119	80119	0	100	300	100	200	200	0	0	80001	0	0	80100
80206	1280760	80135	80135	0	100	300	100	200	200	0	0	80017	0	0	80100
80206	1280722	80133	80133	0	100	300	100	200	200	0	0	80001	0	0	80100
80206	1280769	80134	80134	0	100	300	100	200	200	0	0	80033	0	0	80100
80205	1280387	80117	80117	0	100	300	100	200	200	0	0	80101	0	0	80100
80205	1280722	80134	80134	0	100	300	100	200	204	0	0	80867	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 16.0054

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	1280071	80011	80011	0	10	30	10	20	20	80017	80010
80024	1280077	80011	80011	0	10	30	10	20	20	80019	80010
80024	1280072	80011	80011	0	10	30	10	20	20	80020	80010
80024	1280090	80011	80011	0	10	30	10	20	20	80019	80010
80024	1280071	80011	80011	0	10	30	10	20	20	80019	80010
80024	1280081	80011	80011	0	10	30	10	20	20	80032	80010
80024	1280073	80011	80011	0	10	30	10	20	20	80019	80010
80024	1280101	80011	80011	0	10	30	10	20	20	80019	80010
80024	1280103	80011	80011	0	10	30	10	20	20	80019	80010
80024	1280074	80011	80011	0	10	30	10	20	20	80017	80010

MRS (CNTFRQ_EL0)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations