Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDP (64-bit)

Test 1: uops

Code:

  ldp x0, x1, [x6]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
200572510311103010006242100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
502057014840108301071000130130100031858002710852401063021220008602242000803000310000040100
502047004740103301031000030103100031858478711021401063021220008602242000803000310000040100
502047004740103301031000030103100031858478711021401063021220008602242000803000310000040100
502047004740103301031000030103100031858478711021401063021220008602242000803000310000040100
502047004740103301031000030103100031858478711021401063021220008602242000803000310000040100
502047004740103301031000030103100031858478711021401063021220008602242000803000310000040100
502047004740103301031000030103100031858478711021401063021220008602242000803000310000040100
502047006840104301041000030103100031858049710812401063021220008602242000803000310000040100
502047004740103301031000030103100031858478711021401063021220008602242000803000310000040100
502047004740103301031000030103100031858478711021401063021220008602242000803000310000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0048

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002570152400183001710001300401000018577837114094001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002570087400223002010002300451000018597327123024001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002570084400223002010002300451000018598947123724001030020200006002020000300031000040010
5002470048400133001310000300101000018590577120214001030020200006002020000300031000040010
5002470049400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502057014940108301070100013013001000318562057103004010630212200086022420008300021000040100
502047004240102301020100003010301000318583437109714010630212200086022420008300021000040100
502047004240102301020100003010301000318583437109714010630212200086022420008300021000040100
502057007240110301080100023013501000318591267112964010630212200086022420008300021000040100
502047004240102301020100003010301000318583707109814010630212200086022420008300021000040100
502047004240102301020100003010301000318583437109714010630212200086022420008300021000040100
502047004240102301020100003010301000318583437109714010630212200086022420008300021000040100
502047004240102301020100003010301000318583437109714010630212200086022420008300021000040100
502047004340102301020100003010301000318583437109714010630212200086022420008300021000040100
502047004240102301020100003010301000318583437109714010630212200086022420008300021000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002570154400183001710001300401000018581187117234001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470050400133001310000300101000018589767119864001030020200006002020000300031000040010
5002470049400133001310000300101079418841727218754202631732209466002020000300031000040010
5002470052400133001310000300101000018589497119754001030020200006002020000300031000040010
5002570156400213001910002300441000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010

Test 4: throughput

Count: 8

Code:

  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205402728013510180034100800553072454858015720216011020016002418000080100
160204401008010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800563002548278015620016011220016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160205401468013910180038100800123004467208011220016002420016002418000080100
160204401028010810180007100800123002546008011220016002420016002418000080100
160204400988010910180008100800933072549948019520216018620016002418000080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1600254063280047118003610800123024238280022201600242016000018000080010
1600244007480011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010