Icestorm: STRB (post-index) measurements

Code:

  strb w0, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1276	2059	1041	1018	1040	1000	4641	17677	2000	1000	2000	1001	1000
1004	1081	2001	1001	1000	1000	1000	4641	17551	2000	1000	2000	1001	1000
1004	1110	2001	1001	1000	1000	1000	4641	17587	2000	1000	2000	1001	1000
1004	1080	2001	1001	1000	1000	1000	4641	18181	2000	1000	2000	1001	1000
1004	1082	2001	1001	1000	1000	1000	4641	17569	2000	1000	2000	1001	1000
1004	1073	2001	1001	1000	1000	1000	4641	17569	2000	1000	2000	1001	1000
1004	1077	2001	1001	1000	1000	1000	4641	18217	2000	1000	2000	1001	1000
1004	1077	2001	1001	1000	1000	1000	4637	17713	2000	1000	2000	1001	1000
1004	1078	2001	1001	1000	1000	1000	4641	17533	2000	1000	2000	1001	1000
1004	1085	2001	1001	1000	1000	1000	4641	17659	2000	1000	2000	1001	1000

Test 2: Latency 2->2

Code:

  strb w0, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0125

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11555	20400	10310	10090	10310	10003	72251	171057	20109	200	10010	200	20020	10005	10000	100
10205	10198	20155	10137	10018	10140	10002	43546	171835	20106	200	10008	200	20016	10004	10000	100
10204	10127	20104	10104	10000	10104	10002	43618	171403	20106	200	10008	200	20016	10003	10000	100
10204	10186	20104	10104	10000	10104	10003	47737	172022	20109	200	10010	200	20020	10005	10000	100
10204	10156	20104	10104	10000	10104	10002	43589	171925	20106	200	10008	200	20016	10004	10000	100
10204	10125	20104	10104	10000	10104	10002	43651	171493	20106	200	10008	200	20016	10004	10000	100
10204	10125	20104	10104	10000	10104	10002	43651	171493	20106	200	10008	200	20016	10004	10000	100
10204	10125	20104	10104	10000	10104	10002	43651	171493	20106	200	10008	200	20016	10004	10000	100
10204	10125	20104	10104	10000	10104	10002	43651	171493	20106	200	10008	200	20016	10004	10000	100
10204	10125	20104	10104	10000	10104	10002	43651	171493	20106	200	10008	200	20016	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0111

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11408	20304	10214	10090	10214	10002	43005	171241	20016	20	10008	20	20020	10005	10000	10
10024	10119	20015	10015	10000	10016	10000	42990	171307	20010	20	10000	20	20000	10001	10000	10
10024	10118	20011	10011	10000	10010	10000	42992	171523	20010	20	10000	20	20000	10001	10000	10
10024	10116	20011	10011	10000	10010	10000	42991	171253	20010	20	10000	20	20000	10001	10000	10
10024	10106	20011	10011	10000	10010	10000	42967	171181	20010	20	10000	20	20000	10001	10000	10
10024	10116	20011	10011	10000	10010	10000	42989	171487	20010	20	10000	20	20000	10001	10000	10
10024	10111	20011	10011	10000	10010	10000	42991	171271	20010	20	10000	20	20000	10001	10000	10
10024	10108	20011	10011	10000	10010	10000	42993	171181	20010	20	10000	20	20000	10001	10000	10
10024	10140	20011	10011	10000	10010	10000	42973	171739	20010	20	10000	20	20000	10001	10000	10
10024	10130	20011	10011	10000	10010	10000	42992	171883	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  strb w0, [x6], #8
  strb w0, [x7], #8
  strb w0, [x8], #8
  strb w0, [x9], #8
  strb w0, [x10], #8
  strb w0, [x11], #8
  strb w0, [x12], #8
  strb w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80209	80922	160401	80311	80090	80311	80003	240318	1360063	160109	200	80010	200	160016	0	80005	80000	0	100
80204	80056	160105	80105	80000	80104	80002	240312	1360707	160106	200	80008	200	160016	0	80005	80000	0	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	160016	0	80005	80000	0	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	160016	0	80005	80000	0	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	160340	0	80166	80000	0	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	160016	0	80005	80000	0	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	160016	0	80005	80000	0	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	160016	0	80005	80000	0	100
80204	80053	160105	80105	80000	80104	80002	240312	1360157	160106	200	80008	200	160016	0	80005	80000	0	100
80204	80441	160337	80265	80072	80264	80035	240419	1360825	160175	200	80048	200	160016	0	80005	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	80995	160305	80215	80090	80214	80002	240042	1360319	160016	20	80008	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80025	80103	160065	80048	80017	80052	80000	240030	1359996	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1360045	160010	20	80000	20	160096	80037	80000	10
80024	80048	160011	80011	80000	80010	80035	240149	1360665	160085	20	80048	20	160000	80001	80000	10
80025	80108	160064	80047	80017	80050	80000	240030	1360045	160010	20	80000	20	160000	80001	80000	10

STRB (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations