Icestorm: SUB (shifted immediate, 64-bit) measurements

Code:

  sub x0, x0, #3, lsl #12

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	1000	1001	1000

Test 2: Latency 1->2

Code:

  sub x0, x0, #3, lsl #12

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	259329	10107	10214	10260	10015	10100
10204	10030	10101	10101	10107	259415	10107	10214	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	10212	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	0	10028	259528	10030	10038	10034	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010
10024	10030	10021	10021	0	10020	259591	10020	10020	10020	10011	10010

Test 3: throughput

Count: 8

Code:

  sub x0, x8, #3, lsl #12
  sub x1, x8, #3, lsl #12
  sub x2, x8, #3, lsl #12
  sub x3, x8, #3, lsl #12
  sub x4, x8, #3, lsl #12
  sub x5, x8, #3, lsl #12
  sub x6, x8, #3, lsl #12
  sub x7, x8, #3, lsl #12

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26874	80115	80115	80120	240360	80120	80222	80222	80015	80100
80204	26767	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240504	80171	80276	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	80224	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	28073	80038	80038	80043	266811	80042	80044	80046	80028	80010
80024	26758	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010
80024	26713	80021	80021	80020	277404	80020	80020	80020	80011	80010

SUB (shifted immediate, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations