Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
caspa x0, x1, x2, x3, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 6.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 76007 | 34691 | 3007 | 1 | 0 | 3006 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34438 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34472 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3003 | 11011 | 3003 | 2002 | 4004 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34485 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34456 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34436 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34463 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34443 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34430 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
| 76004 | 34452 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 11001 | 3000 | 2000 | 4000 | 2000 | 7000 | 1 | 3000 | 3000 |
Code:
caspa x0, x1, x2, x3, [x6] add x6, x6, 16
(fused SUBS/B.cc loop)
Result (median cycles for code): 17.0058
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 70234 | 171057 | 51275 | 21169 | 30106 | 21038 | 30036 | 63616 | 645052 | 51113 | 30235 | 40048 | 30202 | 70007 | 0 | 22734 | 30000 | 0 | 40100 |
| 70204 | 170058 | 52835 | 22834 | 30001 | 22827 | 30003 | 68755 | 644734 | 52830 | 30202 | 40004 | 30235 | 70084 | 0 | 21460 | 30000 | 0 | 40100 |
| 70204 | 170530 | 53044 | 22927 | 30117 | 22920 | 30003 | 69147 | 645491 | 52830 | 30202 | 40004 | 30202 | 70007 | 0 | 22734 | 30000 | 0 | 40100 |
| 70204 | 170055 | 52835 | 22834 | 30001 | 22827 | 30003 | 68755 | 644734 | 52830 | 30202 | 40004 | 30235 | 70084 | 0 | 21986 | 30000 | 0 | 40100 |
| 70204 | 170423 | 52990 | 22902 | 30088 | 22895 | 30102 | 69196 | 646310 | 53001 | 30303 | 40136 | 30468 | 70623 | 0 | 22914 | 30000 | 0 | 40100 |
| 70205 | 170344 | 52281 | 22193 | 30088 | 22186 | 30003 | 68755 | 644734 | 52830 | 30202 | 40004 | 30301 | 70238 | 0 | 22803 | 30000 | 0 | 40100 |
| 70204 | 170058 | 52835 | 22834 | 30001 | 22827 | 30069 | 69077 | 645762 | 52941 | 30268 | 40092 | 30301 | 70238 | 0 | 22566 | 30000 | 0 | 40100 |
| 70204 | 170797 | 53094 | 22948 | 30146 | 22941 | 30993 | 73416 | 663963 | 54500 | 31198 | 41324 | 30202 | 70007 | 0 | 22740 | 30000 | 0 | 40100 |
| 70204 | 170058 | 52835 | 22834 | 30001 | 22827 | 30003 | 68741 | 644818 | 52830 | 30202 | 40004 | 38019 | 57394 | 161 | 20811 | 25204 | 117 | 34351 |
| 70204 | 170061 | 52837 | 22836 | 30001 | 22827 | 30003 | 68755 | 644734 | 52830 | 30202 | 40004 | 30202 | 70007 | 0 | 22734 | 30000 | 0 | 40100 |
Result (median cycles for code): 17.0075
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 70055 | 171213 | 51232 | 21096 | 0 | 30136 | 20969 | 0 | 30003 | 69088 | 645404 | 52740 | 30022 | 40004 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
| 70024 | 170070 | 52750 | 22750 | 0 | 30000 | 22737 | 0 | 30000 | 68779 | 644968 | 52737 | 30020 | 40000 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
| 70024 | 170070 | 52750 | 22750 | 0 | 30000 | 22737 | 0 | 30036 | 66068 | 645262 | 51814 | 30055 | 40048 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
| 70024 | 170070 | 52750 | 22750 | 0 | 30000 | 22737 | 0 | 30036 | 64578 | 645190 | 51353 | 30055 | 40048 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
| 70024 | 170083 | 52746 | 22746 | 0 | 30000 | 22737 | 0 | 30000 | 68779 | 644990 | 52737 | 30020 | 40000 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
| 70024 | 170070 | 52750 | 22750 | 0 | 30000 | 22737 | 0 | 30000 | 68779 | 644978 | 52737 | 30020 | 40000 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
| 70024 | 170076 | 52750 | 22750 | 0 | 30000 | 22737 | 0 | 30000 | 68779 | 644979 | 52737 | 30020 | 40000 | 30055 | 70084 | 0 | 22387 | 30000 | 0 | 40010 |
| 70024 | 170068 | 52750 | 22750 | 0 | 30000 | 22737 | 0 | 30000 | 68779 | 644968 | 52737 | 30020 | 40000 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
| 70024 | 170070 | 52750 | 22750 | 0 | 30000 | 22737 | 0 | 30000 | 68779 | 644977 | 52737 | 30020 | 40000 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
| 70024 | 170075 | 52750 | 22750 | 0 | 30000 | 22737 | 0 | 30000 | 68779 | 645089 | 52737 | 30020 | 40000 | 30020 | 70000 | 0 | 22740 | 30000 | 0 | 40010 |
Code:
caspa x0, x1, x2, x3, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 15.0048
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 60209 | 150153 | 51992 | 21955 | 30037 | 11032 | 30003 | 1781570 | 1694391 | 42832 | 20202 | 40004 | 20202 | 70007 | 25453 | 30000 | 30100 |
| 60204 | 150046 | 55556 | 25555 | 30001 | 12827 | 30003 | 1781590 | 1694433 | 42830 | 20202 | 40004 | 20202 | 70007 | 25455 | 30000 | 30100 |
| 60207 | 150089 | 54061 | 24030 | 30031 | 12079 | 30030 | 1781143 | 1694258 | 42867 | 20220 | 40040 | 20202 | 70007 | 25455 | 30000 | 30100 |
| 60204 | 150046 | 55556 | 25555 | 30001 | 12827 | 30003 | 1781590 | 1694433 | 42830 | 20202 | 40004 | 20202 | 70007 | 25455 | 30000 | 30100 |
| 60204 | 150046 | 55556 | 25555 | 30001 | 12827 | 30003 | 1781590 | 1694433 | 42830 | 20202 | 40004 | 20202 | 70007 | 25455 | 30000 | 30100 |
| 60204 | 150046 | 55556 | 25555 | 30001 | 12827 | 30003 | 1781590 | 1694433 | 42830 | 20202 | 40004 | 20202 | 70007 | 25455 | 30000 | 30100 |
| 60207 | 150089 | 53877 | 23845 | 30032 | 11985 | 30030 | 1781143 | 1694258 | 42867 | 20220 | 40040 | 20202 | 70007 | 25455 | 30000 | 30100 |
| 60204 | 150046 | 55556 | 25555 | 30001 | 12827 | 30003 | 1781590 | 1694433 | 42830 | 20202 | 40004 | 20202 | 70007 | 25455 | 30000 | 30100 |
| 60204 | 150046 | 55556 | 25555 | 30001 | 12827 | 30003 | 1781590 | 1694433 | 42830 | 20202 | 40004 | 20202 | 70007 | 25455 | 30000 | 30100 |
| 60204 | 150046 | 55556 | 25555 | 30001 | 12827 | 30003 | 1781590 | 1694433 | 42830 | 20202 | 40004 | 20202 | 70007 | 25455 | 30000 | 30100 |
Result (median cycles for code): 15.0081
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 60029 | 150159 | 51901 | 21863 | 30038 | 10942 | 30069 | 1603196 | 1693901 | 41555 | 20068 | 40092 | 20040 | 70070 | 25456 | 30000 | 30014 |
| 60028 | 150052 | 55484 | 25466 | 30018 | 12746 | 30027 | 1780865 | 1694424 | 42773 | 20038 | 40036 | 20038 | 70063 | 25456 | 30000 | 30014 |
| 60028 | 150052 | 55484 | 25466 | 30018 | 12746 | 30027 | 1780865 | 1694424 | 42773 | 20038 | 40036 | 20038 | 70063 | 25456 | 30000 | 30014 |
| 60028 | 150076 | 55480 | 25462 | 30018 | 12746 | 30021 | 1781275 | 1694963 | 42767 | 20034 | 40028 | 20138 | 70413 | 25466 | 30000 | 30020 |
| 60026 | 150086 | 55478 | 25462 | 30016 | 12746 | 30069 | 1555750 | 1693380 | 41218 | 20066 | 40092 | 20034 | 70049 | 25452 | 30000 | 30012 |
| 60026 | 150078 | 55478 | 25462 | 30016 | 12746 | 30021 | 1781195 | 1694888 | 42767 | 20034 | 40028 | 20086 | 70231 | 25462 | 30000 | 30016 |
| 60026 | 150082 | 55478 | 25462 | 30016 | 12746 | 30021 | 1781195 | 1694888 | 42767 | 20034 | 40028 | 20034 | 70049 | 25452 | 30000 | 30012 |
| 60026 | 150083 | 55478 | 25462 | 30016 | 12746 | 30177 | 1786262 | 1697639 | 42969 | 20138 | 40236 | 20038 | 70063 | 25452 | 30000 | 30014 |
| 60029 | 150122 | 55410 | 25362 | 30048 | 12712 | 30057 | 1728627 | 1694885 | 42436 | 20058 | 40076 | 20034 | 70049 | 25452 | 30000 | 30012 |
| 60026 | 150076 | 55478 | 25462 | 30016 | 12746 | 30021 | 1781207 | 1694907 | 42767 | 20034 | 40028 | 20132 | 70392 | 25461 | 30000 | 30024 |