Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
swpa x0, x1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 72005 | 34374 | 2005 | 1 | 2004 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34129 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34127 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34128 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34400 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34131 | 2001 | 1 | 2000 | 2000 | 11798 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34727 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34247 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34127 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34170 | 2001 | 1 | 2000 | 2000 | 11772 | 2000 | 2000 | 4000 | 1 | 2000 |
Code:
swpa x0, x1, [x6] add x6, x6, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 6.0022
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30209 | 60589 | 30219 | 10138 | 0 | 20081 | 10139 | 0 | 20004 | 35252 | 126744 | 30106 | 10202 | 20004 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60025 | 30103 | 10101 | 0 | 20002 | 10102 | 0 | 20004 | 35252 | 126892 | 30106 | 10202 | 20004 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30205 | 60029 | 30113 | 10105 | 0 | 20008 | 10105 | 0 | 20002 | 35249 | 126819 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 126906 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 126918 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 126906 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 126898 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 126882 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20010 | 35317 | 127324 | 30115 | 10205 | 20011 | 10201 | 40005 | 10001 | 20000 | 10100 |
| 30204 | 60019 | 30101 | 10101 | 0 | 20000 | 10101 | 0 | 20002 | 35249 | 126906 | 30103 | 10201 | 20003 | 10201 | 40005 | 10001 | 20000 | 10100 |
Result (median cycles for code): 6.0015
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30029 | 60581 | 30120 | 10045 | 20075 | 10045 | 20002 | 35069 | 127145 | 30013 | 10021 | 20003 | 10026 | 40024 | 10005 | 20000 | 10010 |
| 30024 | 60028 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 126815 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 126769 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 126825 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 126883 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 126764 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60022 | 30011 | 10011 | 20000 | 10010 | 20000 | 35050 | 127020 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60015 | 30011 | 10011 | 20000 | 10010 | 20010 | 35080 | 127377 | 30025 | 10025 | 20011 | 10025 | 40021 | 10005 | 20000 | 10010 |
| 30025 | 60032 | 30031 | 10017 | 20014 | 10017 | 20002 | 35069 | 127495 | 30013 | 10021 | 20003 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 60019 | 30011 | 10011 | 20000 | 10010 | 20002 | 35069 | 127194 | 30013 | 10021 | 20003 | 10021 | 40005 | 10001 | 20000 | 10010 |
Code:
swpa x0, x1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 22.0039
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20205 | 220150 | 20127 | 101 | 20026 | 100 | 20004 | 300 | 2175602 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40048 | 1 | 20000 | 100 |
| 20204 | 220046 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220039 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220039 | 20105 | 101 | 20004 | 100 | 20024 | 300 | 2175708 | 0 | 20124 | 200 | 20024 | 0 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220039 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175541 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220039 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175581 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220044 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2176360 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 220037 | 20105 | 101 | 20004 | 100 | 20004 | 300 | 2175525 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40008 | 1 | 20000 | 100 |
| 20205 | 220065 | 20125 | 101 | 20024 | 100 | 20004 | 300 | 2175584 | 0 | 20104 | 200 | 20004 | 0 | 200 | 40008 | 1 | 20000 | 100 |
Result (median cycles for code): 22.0044
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20026 | 220173 | 20054 | 11 | 20043 | 10 | 20004 | 30 | 2172801 | 20014 | 20 | 20004 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20024 | 30 | 2173530 | 20034 | 20 | 20024 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220045 | 20011 | 11 | 20000 | 10 | 20026 | 30 | 2172934 | 20036 | 20 | 20026 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20025 | 220111 | 20037 | 11 | 20026 | 10 | 20000 | 30 | 2172678 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 220044 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 2172783 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |