Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (literal, 64-bit)

Test 1: uops

Code:

  ldr x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	945	1001	1	1000	1000	11097	1000	1000	1	1000
1004	715	1001	1	1000	1000	11022	1000	1000	1	1000
1004	719	1001	1	1000	1000	11153	1000	1000	1	1000
1004	717	1001	1	1000	1000	10961	1000	1000	1	1000
1004	702	1001	1	1000	1000	11109	1000	1000	1	1000
1004	725	1001	1	1000	1000	10971	1000	1000	1	1000
1004	725	1001	1	1000	1000	10927	1000	1000	1	1000
1004	712	1001	1	1000	1000	11152	1000	1000	1	1000
1004	721	1001	1	1000	1000	11134	1000	1000	1	1000
1004	717	1001	1	1000	1000	11207	1000	1000	1	1000

Test 2: throughput

Count: 8

Code:

  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4
  ldr x0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5022

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40320	80101	101	80000	100	80008	300	642356	80108	200	80012	200	1	80000	100
80204	40232	80107	101	80006	100	80008	300	643022	80108	200	80012	200	1	80000	100
80204	40169	80101	101	80000	100	80010	300	486266	80110	200	80014	200	1	80000	100
80204	40158	80101	101	80000	100	80008	300	642314	80108	200	80012	200	1	80000	100
80204	40157	80101	101	80000	100	80008	303	642896	80108	200	80012	200	1	80000	100
80204	40206	80101	101	80000	100	80008	300	642224	80108	200	80012	200	1	80000	100
80204	40168	80101	101	80000	100	80008	300	642158	80108	200	80012	200	1	80000	100
80204	40152	80101	101	80000	100	80008	300	642260	80108	200	80012	200	1	80000	100
80204	40164	80101	101	80000	100	80008	300	642158	80108	200	80012	200	1	80000	100
80204	40164	80101	101	80000	100	80008	300	641990	80108	200	80012	200	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5201

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80024	43704	80011	11	80000	10	80000	30	657046	80010	20	80000	20	1	80000	10
80024	41674	80011	11	80000	10	80000	30	667511	80010	20	80000	20	1	80000	10
80024	41599	80011	11	80000	10	80000	30	667855	80010	20	80000	20	1	80000	10
80024	41606	80011	11	80000	10	80000	30	667592	80010	20	80000	20	1	80000	10
80024	41585	80011	11	80000	10	80000	30	667519	80010	20	80000	20	1	80000	10
80024	41617	80011	11	80000	10	80000	30	667875	80010	20	80000	20	1	80000	10
80024	41611	80011	11	80000	10	80000	30	667929	80010	20	80000	20	1	80000	10
80024	41580	80011	11	80000	10	80000	30	667195	80010	20	80000	20	1	80000	10
80024	41609	80011	11	80000	10	80000	30	667447	80010	20	80000	20	1	80000	10
80024	41617	80011	11	80000	10	80000	30	667282	80010	20	80000	20	1	80000	10