Icestorm: SUB (sxtb, 64-bit) measurements

Code:

  sub x0, x0, w1, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Code:

  sub x0, x0, w1, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529083	10104	10210	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529276	10025	10032	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010

Test 3: Latency 1->3

Code:

  sub x0, x1, w0, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	0	529143	0	10104	10210	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20220	20001	10100
10204	20030	20101	20101	10104	702	553808	8773	11912	11813	808	20220	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100
10204	20030	20101	20101	10104	0	529186	0	10104	10212	0	20224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529197	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10025	20060	20035	20035	10058	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010

Test 4: throughput

Count: 8

Code:

  sub x0, x8, w9, sxtb
  sub x1, x8, w9, sxtb
  sub x2, x8, w9, sxtb
  sub x3, x8, w9, sxtb
  sub x4, x8, w9, sxtb
  sub x5, x8, w9, sxtb
  sub x6, x8, w9, sxtb
  sub x7, x8, w9, sxtb

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	53429	160118	160118	80131	1360556	80129	80234	160272	0	0	160017	0	0	80100
80204	53415	160116	160116	80129	1360563	80129	80234	160374	0	0	160060	0	0	80100
80204	53413	160115	160115	80129	1360838	80130	80236	172997	10415	100	166150	4038	43	86723
80204	53404	160117	160117	80130	1360838	80130	80236	160272	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	160272	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	160272	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	160272	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	160272	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	1360838	80130	80236	160272	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	1361149	80177	80289	160272	0	0	160017	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53402	160039	160039	80051	1359975	80051	80056	160020	160011	80010
80025	53408	160081	160081	80096	1359903	80020	80020	160094	160029	80010
80024	53378	160039	160039	80051	1359903	80020	80020	160020	160011	80010
80024	53579	160287	160287	80232	1359903	80020	80020	160126	160076	80010
80024	53371	160021	160021	80020	1360142	80070	80070	160020	160011	80010
80024	53371	160021	160021	80020	1359903	80020	80020	160228	160143	80010
80024	53371	160021	160021	80020	1360111	80073	80074	160020	160011	80010
80024	53371	160021	160021	80020	1360426	80123	80124	160020	160011	80010
80024	53371	160021	160021	80020	1360578	80122	80122	160020	160011	80010
80024	53557	160154	160154	80124	1361965	80380	80382	160964	160598	80010

SUB (sxtb, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations