Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLRH

Test 1: uops

Code:

  stlrh w0, [x6]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056457101911018100010469410001000200011000
10046063100111000100010469410001000200011000
10046063100111000100010469410001000200011000
10046063100111000100010469410001000200011000
10046063100111000100010469410001000200011000
10046063100111000100010469410001000200011000
10046063100111000100010469410001000200011000
10046063100111000100010469410001000200011000
10046063100111000100010469410001000200011000
10046063100111000100010469410001000200011000

Test 2: throughput

Count: 8

Code:

  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  stlrh w0, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 6.0008

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020548015080119101800181008000030085575888010020080004200160104180000100
8020448006580101101800001008000030085575888010020080004200160008180000100
8020648014080139103800361028000030085575888010020080004200160008180000100
8020448005880101101800001008003630085579848013620080052200160008180000100
8020448005880101101800001008000030085575888010020080004200160104180000100
8020448005880101101800001008003630085580208013620080052200160008180000100
8020548009880119101800181008000030085575888010020080004200160008180000100
8020448005880101101800001008003630085580208013620080052200160008180000100
8020448005880101101800001008003630085579128013620080052200160102180000100
8020548011180119101800181008000030085576948010020080004200160008180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 6.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002548015080029118001810800003085576948001020800002016009018000010
8002448006380011118000010800363085578768004620800522016000018000010
8002448005680011118000010800003085575528001020800002016010418000010
8002448005680011118000010800003085575528001020800002016000018000010
8002648014280047118003610800003085575528001020800002016000018000010
8002448005680011118000010800363085578768004620800512016000018000010
8002448005680011118000010800003085575528001020800002016010218000010
8002448005680011118000010800003085575528001020800002016009018000010
8002648014980047118003610800003085575528001020800002016000018000010
8002448005680011118000010800363085580028004620800522016000018000010