Icestorm: LDRSH (unsigned offset, 32-bit) measurements

Code:

  ldrsh w0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	654	1027	1	1026	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40206	70276	40116	30113	10003	30162	10003	1859485	693973	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859446	694015	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1861120	694690	40106	30212	10004	60224	10004	30002	10000	30100
40204	70054	40102	30102	10000	30103	10003	1859743	694135	40106	30212	10004	60294	10017	30008	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70155	40018	30017	10001	30040	10000	1860489	695062	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859787	694776	40010	30020	10000	60322	10052	30039	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40025	70070	40020	30018	10002	30045	10000	1859463	694644	40010	30020	10000	60020	10000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859544	694677	40010	30020	10000	60020	10000	30002	10000	30010

Test 3: throughput

Count: 8

Code:

  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]
  ldrsh w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40184	80127	101	80026	100	80008	300	248262	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80072	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40867	80035	11	80024	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80057	30	640743	80067	20	80069	20	80000	1	80000	10
80024	40053	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40055	80011	11	80000	10	80000	30	640256	80010	20	80000	20	80000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10

LDRSH (unsigned offset, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations