Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLIL2STRM)

Test 1: uops

Code:

  prfm plil2strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2124	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2119	1001	1	1000	1000	35472	1000	1000	1000	1	1000
1004	2118	1001	1	1000	1000	35418	1000	1000	1000	1	1000
1004	2118	1001	1	1000	1000	35462	1000	1000	1000	1	1000
1004	2119	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm plil2strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0215

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	21138	20102	10102	10000	10101	10006	61184	351793	20117	10213	10013	10214	10014	10006	10000	10100
20204	20215	20106	10106	10000	10112	10006	61149	351843	20118	10214	10014	10214	10014	10006	10000	10100
20204	20215	20106	10106	10000	10112	10006	61149	351843	20118	10214	10014	10214	10014	10006	10000	10100
20204	20136	20103	10103	10000	10108	10000	61447	350269	20104	10206	10006	10206	10006	10002	10000	10100
20204	20118	20106	10106	10000	10112	10006	61149	351843	20118	10214	10014	10214	10014	10006	10000	10100
20204	20215	20106	10106	10000	10112	10006	61149	351843	20118	10214	10014	10214	10014	10006	10000	10100
20204	20215	20106	10106	10000	10112	10006	61149	351843	20118	10214	10014	10214	10014	10006	10000	10100
20204	20215	20106	10106	10000	10112	10006	61149	351843	20118	10214	10014	10214	10014	10006	10000	10100
20204	20215	20106	10106	10000	10112	10006	61149	351843	20118	10214	10014	10214	10014	10006	10000	10100
20204	20215	20106	10106	10000	10112	10006	61149	351843	20118	10214	10014	10214	10014	10006	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0056

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20967	20016	10016	10000	10022	10006	61075	349457	20028	10034	10014	10020	10000	10001	10000	10010
20024	19896	20011	10011	10000	10010	10000	61019	349399	20010	10020	10000	10020	10000	10001	10000	10010
20024	20056	20011	10011	10000	10010	10000	61019	349421	20010	10020	10000	10020	10000	10001	10000	10010
20024	20056	20011	10011	10000	10010	10000	61019	349421	20010	10020	10000	10020	10000	10001	10000	10010
20024	20056	20011	10011	10000	10010	10000	61019	349421	20010	10020	10000	10020	10000	10001	10000	10010
20024	20056	20011	10011	10000	10010	10000	61019	349421	20010	10020	10000	10020	10000	10001	10000	10010
20024	20056	20011	10011	10000	10010	10000	61019	349421	20010	10020	10000	10020	10000	10001	10000	10010
20024	20056	20011	10011	10000	10010	10000	61152	347169	20010	10020	10000	10020	10000	10001	10000	10010
20024	20015	20011	10011	10000	10010	10000	61214	346911	20010	10020	10000	10020	10000	10001	10000	10010
20024	19969	20011	10011	10000	10010	10000	61506	347537	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm plil2strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0069

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20082	10101	101	10000	100	10000	300	349212	10100	200	10008	200	10008	1	10000	100
10204	20079	10101	101	10000	100	10000	300	349778	10100	200	10008	200	10008	1	10000	100
10204	20076	10101	101	10000	100	10000	300	349738	10100	200	10008	200	10008	1	10000	100
10204	20072	10101	101	10000	100	10000	300	349468	10100	200	10008	200	10004	1	10000	100
10204	20092	10101	101	10000	100	10000	300	349730	10100	200	10008	200	10004	1	10000	100
10204	20075	10101	101	10000	100	10000	300	349464	10100	200	10004	200	10004	1	10000	100
10204	20075	10101	101	10000	100	10000	300	349476	10100	200	10004	200	10008	1	10000	100
10204	20073	10101	101	10000	100	10000	300	349612	10100	200	10008	200	10008	1	10000	100
10204	20066	10101	101	10000	100	10006	300	349222	10106	200	10012	200	10012	1	10000	100
10204	20058	10101	101	10000	100	10000	300	349442	10100	200	10004	200	10008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0641

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	19231	10011	11	10000	10	10000	30	328922	10010	20	10004	20	10000	1	10000	10
10024	19380	10011	11	10000	10	10000	30	333686	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18815	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	19524	10011	11	10000	10	10000	30	335714	10010	20	10000	20	10000	1	10000	10
10024	19203	10011	11	10000	10	10000	30	332844	10010	20	10000	20	10072	1	10000	10
10024	19546	10011	11	10000	10	10000	30	334208	10010	20	10000	20	10000	1	10000	10
10024	19424	10011	11	10000	10	10000	30	326766	10010	20	10000	20	10000	1	10000	10