Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADD (register, 64-bit)

Test 1: uops

Code:

  add x0, x0, x1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000
100410301001100110002560310001000200010011000

Test 2: Latency 1->2

Code:

  add x0, x0, x1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102041003010101101011010725933010107102142022800100010010100
102041003010101101011010725953910107102122022400100010010100
102041003010101101011010725953910107102122022400100010010100
102041003010101101011010725953910107102122022400100010010100
102041003010101101011010725953910107102122022400100010010100
102041003010101101011010725953910107102122022400100010010100
102041003010101101011010725953910107102122022600100010010100
1020410030101011010110107259435101071021421053577610340285110502
102041003010101101011010725953910107102122022400100010010100
102041003010101101011010725953910107102122022400100010010100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010

Test 3: Latency 1->3

Code:

  add x0, x1, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101072593301010710214202281000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100
10204100301010110101101072595391010710212202241000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282594741002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10024100301002110021100202595911002010020200201001110010
10025100601003510035100692595911002010020200201001110010

Test 4: throughput

Count: 8

Code:

  add x0, x8, x9
  add x1, x8, x9
  add x2, x8, x9
  add x3, x8, x9
  add x4, x8, x9
  add x5, x8, x9
  add x6, x8, x9
  add x7, x8, x9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802042686880115801158012024036080120802221602428001480100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100
802042673780115801158012024036080120802241602488001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800242795680038800388004327748480043800451600208001180010
800242675880021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010
800242675780021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010
800242671380021800218002027740480020800201600208001180010
800242673280021800218002028273880020800201600208001180010
800242671380021800218002028273880020800201600208001180010