Icestorm: STRH (pre-index) measurements

Code:

  strh w0, [x6, #8]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1270	2059	1041	1018	1040	1000	4685	17569	2000	1000	2000	1001	1000
1004	1075	2001	1001	1000	1000	1000	4761	18073	2000	1000	2000	1001	1000
1004	1122	2001	1001	1000	1000	1000	4761	18163	2000	1000	2000	1001	1000
1004	1098	2001	1001	1000	1000	1000	4761	17587	2000	1000	2000	1001	1000
1004	1071	2001	1001	1000	1000	1000	4761	17515	2000	1000	2000	1001	1000
1004	1072	2001	1001	1000	1000	1000	4761	17605	2000	1000	2000	1001	1000
1004	1076	2001	1001	1000	1000	1000	4761	18163	2000	1000	2000	1001	1000
1004	1072	2001	1001	1000	1000	1000	4761	17587	2000	1000	2000	1001	1000
1004	1076	2001	1001	1000	1000	1000	4761	17587	2000	1000	2000	1001	1000
1004	1101	2001	1001	1000	1000	1000	4761	17587	2000	1000	2000	1001	1000

Test 2: Latency 2->2

Code:

  strh w0, [x6, #8]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0095

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11231	20404	10314	10090	10314	10002	43549	171007	20106	200	10008	200	20020	10005	10000	100
10204	10098	20104	10104	10000	10104	10002	43549	171025	20106	200	10008	200	20016	10004	10000	100
10204	10099	20104	10104	10000	10104	10002	43550	171025	20106	200	10008	200	20016	10004	10000	100
10204	10095	20104	10104	10000	10104	10002	43549	171025	20106	200	10008	200	20016	10004	10000	100
10204	10095	20104	10104	10000	10104	10002	43549	171025	20106	200	10008	200	20016	10004	10000	100
10204	10095	20104	10104	10000	10104	10002	43550	171025	20106	200	10008	200	20016	10004	10000	100
10204	10100	20104	10104	10000	10104	10002	43550	171025	20106	200	10008	200	20016	10004	10000	100
10204	10099	20104	10104	10000	10104	10002	43549	171025	20106	200	10008	200	20016	10004	10000	100
10204	10095	20104	10104	10000	10104	10002	43549	171025	20106	200	10008	200	20016	10004	10000	100
10204	10095	20104	10104	10000	10104	10002	43549	171025	20106	200	10008	200	20016	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0100

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11576	20305	10215	10090	10216	10002	63600	170994	20016	20	10008	20	20000	10001	10000	10
10024	10100	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10
10024	10100	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10
10024	10100	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10
10024	10099	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10
10024	10100	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10
10024	10100	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10
10024	10100	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10
10024	10100	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10
10024	10100	20011	10011	10000	10010	10000	43071	171037	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  strh w0, [x6, #8]!
  strh w0, [x7, #8]!
  strh w0, [x8, #8]!
  strh w0, [x9, #8]!
  strh w0, [x10, #8]!
  strh w0, [x11, #8]!
  strh w0, [x12, #8]!
  strh w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	80938	160401	80311	80090	80311	80002	240312	1360157	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359948	160106	200	80008	200	160096	80037	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80035	240419	1361203	160175	200	80048	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160096	80037	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	80959	160305	80215	80090	80214	80002	240042	1360211	160016	20	80008	20	160016	80005	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80025	80115	160064	80047	80017	80050	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160096	80037	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10

STRH (pre-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations