Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (ISHLD)

Test 1: uops

Code:

  dsb ishld

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
1004	16033	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16033	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16028	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16028	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16028	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16028	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16028	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16028	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16028	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0
1004	16028	1001	1	1000	1000	4000	1000	1000	0	0	0	1	1000	0	0

Test 2: throughput

Code:

  dsb ishld

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 16.0028

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	160033	10105	101	10004	100	10006	300	40024	10106	200	10006	200	1	9999	100
10204	160033	10105	101	10004	100	10006	300	40024	10106	200	10006	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	10004	100	10012	303	40048	10113	202	10012	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	10004	100	10012	300	40048	10112	200	10012	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	10104	200	10004	200	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 16.0028

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	160033	10015	11	0	10004	10	0	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160050	10021	11	0	10010	10	0	10004	30	40016	10014	20	10004	20	0	1	10000	0	10
10024	160028	10011	11	0	10000	10	0	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	0	10000	10	0	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	0	10000	10	0	10016	30	40064	10026	20	10016	20	0	1	10000	0	10
10024	160028	10011	11	0	10000	10	0	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	0	10000	10	0	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	0	10000	10	0	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160056	10023	11	0	10012	10	0	10000	30	40000	10010	20	10000	20	0	1	10000	0	10
10024	160028	10011	11	0	10000	10	0	10000	30	40000	10010	20	10000	20	0	1	10000	0	10