Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

AUTIZB

Test 1: uops

Code:

  autizb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	? int output thing (e9)	? int retires (ef)
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000

Test 2: Latency 1->1

Code:

  autizb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10205	60058	10204	10204	10211	530325	10200	200	200	10104	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10025	60058	10024	10024	10031	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	530085	10053	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60196	10037	10037	10068	529944	10034	22	20	10011	10010
10024	60071	10025	10025	10032	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60071	10025	10025	10032	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10019	10010

Test 3: throughput

Count: 8

Code:

  autizb x0
  autizb x1
  autizb x2
  autizb x3
  autizb x4
  autizb x5
  autizb x6
  autizb x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	160030	80201	80201	80202	0	1360430	0	80202	200	0	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	0	1360481	0	80202	200	0	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	0	1360481	0	80202	200	0	200	0	0	80101	0	0	80100
80205	160064	80211	80211	80220	134	1367427	3562	80591	547	162	200	0	0	80127	0	0	80100
80204	160030	80201	80201	80202	0	1360379	0	80202	200	0	200	0	0	80111	0	0	80100
80204	160030	80201	80201	80202	0	1360481	0	80202	200	0	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	0	1360481	0	80202	200	0	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	0	1360481	0	80202	200	0	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	0	1360481	0	80202	200	0	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	0	1360481	0	80202	200	0	200	0	0	80101	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	160030	80021	80021	80022	0	1359890	0	80022	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1360016	0	80037	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80021	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80021	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1360007	0	80040	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010