Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CSET (32-bit)

Test 1: uops

Code:

  cset w0, hi

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	524	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	370	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000

Test 2: Latency 1->2

Chain cycles: 1

Code:

  cset w0, hi
  tst x0, 1

Initialization

  mov x0, 1

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20208	519267	20208	20216	20216	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	20216	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	20216	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	20216	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	20216	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	20216	20101	10100
20205	20060	20215	20215	20251	519448	20208	20216	20216	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	20216	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	20216	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	20216	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20029	519455	20029	20036	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	20020	20011	10010

Test 3: throughput

Count: 8

Code:

  cset w0, hi
  cset w1, hi
  cset w2, hi
  cset w3, hi
  cset w4, hi
  cset w5, hi
  cset w6, hi
  cset w7, hi

Initialization

  mov x0, 0
  cmp x0, x0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26902	80115	80115	80120	292168	80120	80222	80221	80014	80100
80204	26752	80115	80115	80120	293236	80120	80221	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80276	80058	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	274026	80174	80280	80221	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	27985	80038	80038	80051	389437	80020	80020	80020	80011	80010
80024	27064	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26741	80021	80021	80020	426780	80020	80020	80109	80072	80010
80024	26728	80021	80021	80020	426780	80020	80020	80109	80071	80010
80024	26727	80021	80021	80020	426780	80020	80020	80020	80011	80010
80024	26724	80021	80021	80020	426780	80020	80020	80020	80011	80010
80024	26723	80021	80021	80020	426780	80020	80020	80020	80011	80010
80024	26728	80021	80021	80020	426780	80020	80020	80020	80011	80010
80024	26723	80021	80021	80020	426780	80020	80020	80020	80011	80010
80024	26723	80021	80021	80020	426780	80020	80020	80020	80011	80010