Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSW (register, lsl)

Test 1: uops

Code:

  ldrsw x0, [x6, x7, lsl #2]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056461021110201000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570151401083010710001301301000318593506938264010630210100046022420008300021000030100
4020470042401023010210000301031000318611746947174010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470044401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470056401023010210000301031000318595276940464010630212100046022420008300021000030100
4020570072401103010810002301351000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
400257016340018300171000130040100031859434693626040016300301000406004420008300021000030010
400247004040012300121000030010100001859463694644040010300201000006002020000300021000030010
400257007040020300181000230045100001859463694644040010300201000006002020000300021000030010
400247004040012300121000030010100001859463694644040010300201000006002020000300021000030010
400247004040012300121000030010100001859517694666040010300201000006002020000300021000030010
400247004040012300121000030010100001859490694654040010300201000006002020000300021000030010
400247004040012300121000030010100001859463694644040010300201000006002020000300021000030010
400247004040012300121000030010100001859490694655040010300201000006002020000300021000030010
400247004040012300121000030010100001859490694654040010300201000006004420010300041000030010
400247004540012300121000030010159831364465666373173444663141917732196002020000300021000030010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570155401083010710001301301000318594436936914010630210100046022420008300031000030100
4020470049401033010310000301031000318594466940134010630212100046022420008300021000030100
4020570140401103010810002301351000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020570106401103010810002301351000318595336939264010630210100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046022420008300021000030100
4020470042401023010210000301031000318594466940134010630212100046029420034300081000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570369400303002610004300731000018598476937534001030020100006004020008300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470426400613004910012301421000018597066947344001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470049400133001310000300101000018597336947454001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006011620034300091000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470064400133001310000300101000018597336947444001030020100006012220036300091000030010

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205401788013310180032100800083003281728010820080012200160024180000100
80204400528010110180000100800083006401788010820080012200160024180000100
80204400518010110180000100800083006401788010820080012200160024180000100
80204400618010110180000100800083002482268010820080012200160024180000100
80204400478010110180000100800103006401188011020080014200160024180000100
80204400478010110180000100800083006401068010820080012200160028180000100
80204400478010110180000100800083006401068010820080012200160024180000100
80204400478010110180000100800083006401068010820080012200160024180000100
80204400478010110180000100800083006401068010820080012200160024180000100
80204400478010110180000100800083006401068010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025402058004511800341080008304002988001820800122016002818000010
80024400568001111800001080000306402748001020800002016000018000010
80024400568001111800001080000306402748001020800002016000018000010
80024400568001111800001080000306402748001020800002016000018000010
80024400568001111800001080000306402748001020800002016000018000010
80024400568001111800001080000306402748001020800002016000018000010
80024400568001111800001080000306402748001020800002016000018000010
80024400628001111800001080000306404188001020800002016000018000010
80024400698001111800001080000306403288001020800002016013818000010
80024400648001111800001080000306402748001020800002016000018000010