Icestorm: LDRSW (register, lsl) measurements

Code:

  ldrsw x0, [x6, x7, lsl #2]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	646	1021	1	1020	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70151	40108	30107	10001	30130	10003	1859350	693826	40106	30210	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1861174	694717	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70044	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70056	40102	30102	10000	30103	10003	1859527	694046	40106	30212	10004	60224	20008	30002	10000	30100
40205	70072	40110	30108	10002	30135	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70163	40018	30017	10001	30040	10003	1859434	693626	0	40016	30030	10004	0	60044	20008	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40025	70070	40020	30018	10002	30045	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859517	694666	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859490	694654	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859490	694655	0	40010	30020	10000	0	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859490	694654	0	40010	30020	10000	0	60044	20010	30004	10000	30010
40024	70045	40012	30012	10000	30010	15983	1364465	666373	173	44466	31419	17732	19	60020	20000	30002	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70155	40108	30107	10001	30130	10003	1859443	693691	40106	30210	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40205	70140	40110	30108	10002	30135	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40205	70106	40110	30108	10002	30135	10003	1859533	693926	40106	30210	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60294	20034	30008	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70369	40030	30026	10004	30073	10000	1859847	693753	40010	30020	10000	60040	20008	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70426	40061	30049	10012	30142	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859733	694745	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60116	20034	30009	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70064	40013	30013	10000	30010	10000	1859733	694744	40010	30020	10000	60122	20036	30009	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40178	80133	101	80032	100	80008	300	328172	80108	200	80012	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640178	80108	200	80012	200	160024	1	80000	100
80204	40051	80101	101	80000	100	80008	300	640178	80108	200	80012	200	160024	1	80000	100
80204	40061	80101	101	80000	100	80008	300	248226	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80010	300	640118	80110	200	80014	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160028	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640106	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40205	80045	11	80034	10	80008	30	400298	80018	20	80012	20	160028	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10
80024	40062	80011	11	80000	10	80000	30	640418	80010	20	80000	20	160000	1	80000	10
80024	40069	80011	11	80000	10	80000	30	640328	80010	20	80000	20	160138	1	80000	10
80024	40064	80011	11	80000	10	80000	30	640274	80010	20	80000	20	160000	1	80000	10

LDRSW (register, lsl)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations