Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADD (register, lsl, 64-bit)

Test 1: uops

Code:

  add x0, x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000

Test 2: Latency 1->2

Code:

  add x0, x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290661010410210202202000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212203042001510100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292201002510034200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010

Test 3: Latency 1->3

Code:

  add x0, x1, x0, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
102042003020101201010101045291001010410210202242000110100
102042003020101201010101045291861010410212202242000110100
102042003020101201010101045291861010410212202242000110100
102042003020101201010101045291861010410212202242000110100
102042003020101201010101045291861010410212202242000110100
102042003020101201010101045291861010410212202242000110100
102042003020101201010101045291861010410212202242000110100
102042003020101201010101045291861010410212202242000110100
102042003020101201010101045291861010410212202242000110100
102042003020101201010101045291861010410212202242000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292201002510034200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010

Test 4: throughput

Count: 8

Code:

  add x0, x8, x9, lsl #17
  add x1, x8, x9, lsl #17
  add x2, x8, x9, lsl #17
  add x3, x8, x9, lsl #17
  add x4, x8, x9, lsl #17
  add x5, x8, x9, lsl #17
  add x6, x8, x9, lsl #17
  add x7, x8, x9, lsl #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
8020453404160117160117801301360556801298023416026801600160080100
8020453404160117160117801301360838801308023616026801600160080100
8020453404160117160117801301360838801308023616027201600170080100
8020453404160117160117801301360838801308023616027201600170080100
8020453404160117160117801301360838801308023616027201600170080100
8020453404160117160117801301360838801308023616027201600170080100
8020453404160117160117801301360838801308023616027201600170080100
8020453404160117160117801301360838801308023616027201600170080100
8020453404160117160117801301360838801308023616027201600170080100
8020553436160165160165801781360838801308023616027201600170080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002453402160039160039800511359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010