Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (NSHST)

Test 1: uops

Code:

  dsb nshst

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)? int output thing (e9)? ldst retires (ed)
100416033100111000100040001000100011000
100416033100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000
100416028100111000100040001000100011000

Test 2: throughput

Code:

  dsb nshst

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 16.0028

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102041600331010510110004100100063004002401010620010006020001100000100
102041600331010510110004100100043004001601010420010004020001100000100
102041600281010510110004100100043004001601010420010004020001100000100
102041600281010510110004100100043004001601010420010004020001100000100
10204160028101051011000410010004300400160101042001000402000199990100
102041600281010510110004100100043004001601010420010004020001100000100
102041600281010510110004100100043004001601010420010004020001100000100
102041600281010510110004100100043004001601010420010004020001100000100
1020416002810105101100041002622350009834652870224781530836292381454675287220491072322799
102041600281010510110004100100123004004801011220010012020001100000100

1000 unrolls and 10 iterations

Result (median cycles for code): 16.0028

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)? int output thing (e9)? ldst retires (ed)? int retires (ef)
10024160033100151110004101004230403801005220100422011000010
10024160033100111110000101003633404121004722100362011000010
1002416002810011111000010100003040000100102010000201999910
10024160056100261110015101000030400001001020100002011000010
10024160153100441110033101000030400001001020100002011000010
10024160169100491110038101000030400001001020100002011000010
10024160028100111110000101004730405061005720100472011000010
10024160028100111110000101003030401761004020100302011000010
10024160028100111110000101000030400001001020100002011000010
10024160168100451110034101000030400001001020100002011000010