Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLIL1STRM)

Test 1: uops

Code:

  prfm plil1strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2122	1001	1	1000	1000	35216	1000	1000	1000	1	1000
1004	2119	1001	1	1000	1000	35678	1000	1000	1000	1	1000
1004	2113	1001	1	1000	1000	35358	1000	1000	1000	1	1000
1004	2146	1001	1	1000	1000	35472	1000	1000	1000	1	1000
1004	2144	1001	1	1000	1000	35674	1000	1000	1000	1	1000
1004	2119	1001	1	1000	1000	35410	1000	1000	1000	1	1000
1004	2103	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm plil1strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.9617

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	21176	20103	10103	10000	10105	10000	60713	358965	20105	10207	10007	10207	10007	10003	10000	10100
20204	20600	20102	10102	10000	10106	10000	60789	359029	20106	10208	10008	10208	10008	10002	10000	10100
20204	20600	20102	10102	10000	10106	10000	60789	359029	20106	10208	10008	10208	10008	10002	10000	10100
20204	20600	20102	10102	10000	10106	10000	60789	359029	20106	10208	10008	10208	10008	10002	10000	10100
20204	20322	20105	10105	10000	10106	10000	61173	352959	20104	10206	10006	10204	10004	10001	10000	10100
20204	20345	20103	10103	10000	10108	10000	61087	355133	20106	10208	10008	10210	10010	10003	10000	10100
20204	20369	20102	10102	10000	10106	10000	60997	355915	20106	10208	10008	10208	10008	10002	10000	10100
20204	20600	20102	10102	10000	10106	10000	60789	359029	20106	10208	10008	10208	10008	10002	10000	10100
20204	20600	20102	10102	10000	10106	10000	60789	359029	20106	10208	10008	10208	10008	10002	10000	10100
20204	20600	20102	10102	10000	10106	10000	60789	359029	20106	10208	10008	10208	10008	10002	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0168

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	23150	20011	10011	10000	10012	10000	60992	351615	20010	10020	10000	10020	10000	10001	10000	10010
20024	20192	20011	10011	10000	10010	10000	61072	350633	20010	10020	10000	10056	10036	10035	10000	10010
20024	20068	20011	10011	10000	10010	10000	60964	352533	20010	10020	10000	10020	10000	10001	10000	10010
20024	20162	20011	10011	10000	10010	10000	61002	351339	20010	10020	10000	10020	10000	10001	10000	10010
20024	20162	20011	10011	10000	10010	10000	61072	351481	20010	10020	10000	10020	10000	10001	10000	10010
20024	20114	20011	10011	10000	10010	10000	61072	351463	20010	10020	10000	10020	10000	10001	10000	10010
20024	20161	20011	10011	10000	10010	10000	61003	351645	20010	10020	10000	10020	10000	10001	10000	10010
20024	20233	20011	10011	10000	10010	10000	61153	350939	20010	10020	10000	10020	10000	10001	10000	10010
20024	20148	20011	10011	10000	10010	10000	61070	351517	20010	10020	10000	10020	10000	10001	10000	10010
20024	20179	20011	10011	10000	10010	10000	61066	351499	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm plil1strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10205	19718	10133	103	10030	102	10006	300	325210	10106	200	10014	200	10012	1	10000	100
10204	19623	10101	101	10000	100	10006	300	338820	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	200	10012	1	10000	100
10204	18718	10101	101	10000	100	10006	300	325270	10106	200	10012	202	10066	2	10000	100
10204	19088	10101	101	10000	100	10000	300	334798	10100	200	10008	200	10012	1	10000	100
10204	19442	10101	101	10000	100	10000	300	357430	10100	200	10006	200	10004	1	10000	100
10204	20468	10101	101	10000	100	10000	300	356888	10100	200	10008	200	10012	1	10000	100
10204	20427	10101	101	10000	100	10000	300	355474	10100	200	10008	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20803	10011	11	10000	10	10000	30	363498	10010	20	10000	20	10006	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10
10024	20503	10011	11	10000	10	10000	30	357322	10010	20	10000	20	10000	1	10000	10