Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSW (unsigned offset)

Test 1: uops

Code:

  ldrsw x0, [x6, #8]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056641027110261000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40205701544010830107100013013010003185939869396840106302121000460224100043000210000030100
40204700494010230102100003010310003186101269464440106302121000460224100043000210000030100
40204700424010230102100003010310003185944669401340106302121000460224100043000210000030100
40204700424010230102100003010310003186033769437640106302121000460224100043000210000030100
40204700424010230102100003010310003185944669401340106302121000460224100043000210000030100
40204700424010230102100003010310003185944669401340106302121000460224100043000210000030100
40204700424010230102100003010310003185944669401340106302121000460224100043000210000030100
40204700424010230102100003010310003185944669401340106302121000460224100043000210000030100
40204700424010230102100003010310003185944669401340106302121000460224100043000210000030100
40204700424010230102100003010310003185944669401340106302121000460224100043000210000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570358400183001710001300401000318596776947134001630032100046002010000300031000030010
4002470042400123001210000300101000018595176946644001030020100006011410017300091000030010
4002470057400123001210000300101000018595986946974001030020100006002010000300021000030010
4002470046400123001210000300101000018595446946754001030020100006002010000300021000030010
4002470048400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002570072400203001810002300451000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018614346954384001030020100006002010000300021000030010

Test 3: throughput

Count: 8

Code:

  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  ldrsw x0, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540185801271018002610080008300424350801082008001220080012180000100
8020440069801011018000010080008300640196801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100
8020440049801011018000010080008300640142801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540189800391180028108000830400136800182080012208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002540101800461180035108000030641984800102080000208000018000010
8002440061800111180000108000030640166800102080000208000018000010