Icestorm: NGC (register, 32-bit) measurements

Code:

  ngc w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  ngc w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	259311	10107	10214	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	259474	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20148	10025	10010
10024	10030	10021	10021	10020	261452	10196	10206	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Chain cycles: 1

Code:

  ngc w0, w1
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20209	519190	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20209	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	30224	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20029	519455	20029	20036	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	30020	20011	10010

Test 4: throughput

Count: 8

Code:

  ngc w0, w8
  ngc w1, w8
  ngc w2, w8
  ngc w3, w8
  ngc w4, w8
  ngc w5, w8
  ngc w6, w8
  ngc w7, w8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26900	80115	80115	80120	291634	80120	80224	160248	80015	80100
80204	26742	80115	80115	80120	266795	80119	80222	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160244	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	160248	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	27893	80038	80038	80052	328087	80020	80020	160020	80011	80010
80024	26772	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26718	80021	80021	80020	328669	80106	80110	160020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26718	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26960	80185	80185	80184	389437	80020	80020	160020	80011	80010
80024	26718	80021	80021	80020	316726	80103	80105	160020	80011	80010
80024	26718	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26718	80021	80021	80020	389437	80020	80020	160020	80011	80010
80024	26718	80021	80021	80020	389437	80020	80020	160020	80011	80010

NGC (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations