Icestorm: STP (pre-index, 32-bit) measurements

Code:

  stp w0, w1, [x6, #8]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1890	2059	1041	1018	1040	1000	4685	18001	2000	1000	3000	1001	1000
1004	1082	2001	1001	1000	1000	1000	4681	17443	2000	1000	3000	1001	1000
1004	1073	2001	1001	1000	1000	1000	4681	17371	2000	1000	3000	1001	1000
1004	1092	2001	1001	1000	1000	1000	4681	18451	2000	1000	3000	1001	1000
1004	1096	2001	1001	1000	1000	1000	4681	17353	2000	1000	3000	1001	1000
1004	1063	2001	1001	1000	1000	1000	4681	17353	2000	1000	3000	1001	1000
1004	1070	2001	1001	1000	1000	1000	4685	17515	2000	1000	3000	1001	1000
1004	1071	2001	1001	1000	1000	1000	4681	17407	2000	1000	3000	1001	1000
1004	1079	2001	1001	1000	1000	1000	4657	18073	2000	1000	3000	1001	1000
1004	1096	2001	1001	1000	1000	1000	4641	18019	2000	1000	3000	1001	1000

Test 2: Latency 3->3

Code:

  stp w0, w1, [x6, #8]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0087

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11893	20404	10314	10090	10314	10003	107113	170715	20109	200	10010	200	30030	10001	10000	100
10204	10088	20104	10104	10000	10104	10002	43629	170791	20106	200	10008	200	30024	10004	10000	100
10204	10087	20104	10104	10000	10104	10002	43629	170791	20106	200	10008	200	30024	10004	10000	100
10204	10128	20104	10104	10000	10104	10002	43629	171007	20106	200	10008	200	30024	10004	10000	100
10204	10107	20104	10104	10000	10104	10002	43631	170989	20106	200	10008	200	30024	10004	10000	100
10204	10115	20104	10104	10000	10104	10001	43627	171166	20105	200	10008	200	30024	10004	10000	100
10204	10120	20104	10104	10000	10104	10001	43628	171076	20105	200	10008	200	30024	10004	10000	100
10204	10096	20104	10104	10000	10104	10002	43631	171151	20106	200	10008	200	30024	10003	10000	100
10204	10086	20104	10104	10000	10104	10002	43629	170791	20106	200	10008	200	30024	10004	10000	100
10204	10086	20104	10104	10000	10104	10002	43629	170791	20106	200	10008	200	30024	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0094

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11353	20307	10217	10090	10218	10002	43007	170917	20016	20	10008	20	30000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	42995	170929	20010	20	10000	20	30000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	42995	170947	20010	20	10000	20	30000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	42995	170929	20010	20	10000	20	30000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	42995	170929	20010	20	10000	20	30000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	42995	170929	20010	20	10000	20	30000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	42995	170929	20010	20	10000	20	30000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	42995	170929	20010	20	10000	20	30000	10001	10000	10
10024	10094	20011	10011	10000	10010	10000	42995	170929	20010	20	10000	20	30000	10001	10000	10
10024	10093	20011	10011	10000	10010	10000	42991	170875	20010	20	10000	20	30000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  stp w0, w1, [x6, #8]!
  stp w0, w1, [x7, #8]!
  stp w0, w1, [x8, #8]!
  stp w0, w1, [x9, #8]!
  stp w0, w1, [x10, #8]!
  stp w0, w1, [x11, #8]!
  stp w0, w1, [x12, #8]!
  stp w0, w1, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	81553	160401	80311	80090	80311	80002	240312	1360064	160106	200	80008	200	240024	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	240024	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	240024	80005	80000	100
80204	80043	160105	80105	80000	80104	80002	240312	1361923	160106	200	80008	200	240024	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	240024	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	240024	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	240024	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	240024	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	240024	80005	80000	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	160106	200	80008	200	240024	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	80965	160305	80215	80090	80214	80002	240042	1360211	160016	20	80008	20	240024	80005	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240264	80069	80000	10
80024	80056	160011	80011	80000	80010	80035	240149	1360807	160085	20	80048	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240120	80033	80000	10
80025	80115	160064	80047	80017	80050	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	240000	80001	80000	10

STP (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations