Icestorm: CCMP (immediate, 64-bit) measurements

Code:

  ccmp x1, #3, #0, hi

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  ccmp x1, #3, #0, hi
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519435	20107	20212	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519454	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 2->2

Code:

  ccmp x0, #3, #0, hi

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10211	254770	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255557	10068	10072	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10

Test 4: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7889

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63313	160112	160112	160118	690240	160118	160220	160220	160013	100
160204	63111	160115	160115	160120	688477	160118	160220	160216	160011	100
160204	63098	160111	160111	160118	689652	160118	160220	160216	160010	100
160204	63112	160112	160112	160118	689546	160157	160259	160220	160013	100
160204	63175	160110	160110	160116	688591	160120	160220	160224	160014	100
160204	63091	160112	160112	160118	690894	160120	160220	160220	160012	100
160204	63115	160112	160112	160118	689536	160118	160220	160224	160014	100
160204	63134	160115	160115	160120	689652	160118	160220	160220	160012	100
160204	63127	160112	160112	160118	687037	160118	160220	160220	160012	100
160204	63091	160112	160112	160118	691935	160118	160220	160220	160014	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7881

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160958	71727	160913	160582	331	160549	697198	160033	160044	160020	160001	10
160024	64567	160023	160023	0	160030	697503	160026	160038	160038	160011	10
160024	63076	160021	160021	0	160026	699355	160033	160044	160038	160011	10
160024	63049	160011	160011	0	160010	700928	160010	160020	160020	160001	10
160024	63045	160011	160011	0	160010	702064	160010	160020	160020	160001	10
160024	63054	160011	160011	0	160010	696147	160010	160020	160020	160001	10
160025	63198	160053	160053	0	160071	696046	160010	160020	160020	160001	10
160024	63032	160011	160011	0	160010	694168	160010	160020	160020	160001	10
160024	63077	160011	160011	0	160010	700568	160010	160020	160020	160001	10
160024	63040	160011	160011	0	160010	704042	160010	160020	160020	160001	10

Test 5: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24010	50107	40104	10003	40114	10004	315209	40012	50112	40209	10003	80224	20008	40001	100
50204	24001	50109	40105	10004	40116	10004	315522	40017	50116	40212	10004	80224	20008	40002	100
50204	23997	50103	40101	10002	40112	10004	315522	40017	50116	40212	10004	80218	20006	40003	100
50204	23979	50106	40103	10003	40109	10003	314924	40017	50119	40216	10004	80224	20008	40002	100
50204	23997	50103	40101	10002	40112	10004	315522	40017	50116	40212	10004	80218	20006	40001	100
50204	23990	50104	40101	10003	40112	10004	315029	40018	50116	40212	10004	80218	20006	40001	100
50204	23982	50104	40101	10003	40112	10004	315393	40013	50112	40209	10003	80224	20008	40002	100
50204	23981	50106	40103	10003	40109	10003	315122	40016	50120	40216	10004	80224	20008	40002	100
50204	23993	50103	40101	10002	40109	10003	315617	40017	50116	40212	10004	80224	20008	40002	100
50204	23976	50105	40102	10003	40112	10004	315393	40013	50112	40209	10003	80218	20006	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24109	50018	40015	10003	40021	10003	315893	40000	50010	40020	10000	80020	20000	40001	10
50024	24018	50011	40011	10000	40010	10000	316461	40000	50010	40020	10000	80020	20000	40001	10
50024	24001	50011	40011	10000	40010	10000	316578	40000	50010	40020	10000	80054	20010	40008	10
50024	23986	50013	40011	10002	40019	10003	316131	40000	50010	40020	10000	80020	20000	40001	10
50024	24019	50011	40011	10000	40010	10000	316079	40000	50010	40020	10000	80020	20000	40001	10
50024	24277	50168	40137	10031	40136	10031	315621	40000	50010	40020	10000	80020	20000	40001	10
50024	23974	50011	40011	10000	40010	10000	316459	40000	50010	40020	10000	80020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	316681	40000	50010	40020	10000	80020	20000	40001	10
50024	23986	50011	40011	10000	40010	10000	315542	40000	50010	40020	10000	80020	20000	40001	10
50024	24049	50011	40011	10000	40010	10000	315621	40000	50010	40020	10000	80020	20000	40001	10

Test 6: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi
  ccmp x0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	39296	80260	80260	80269	550575	80114	80216	140220	0	0	80004	0	0	100
80204	38984	80105	80105	80112	549185	80108	80208	140220	0	0	80004	0	0	100
80204	38986	80106	80106	80114	550632	80116	80216	140228	0	0	80007	0	0	100
80204	38981	80105	80105	80116	550985	80108	80208	140220	0	0	80006	0	0	100
80204	38974	80109	80109	80116	546380	80152	80252	140228	0	0	80004	0	0	100
80205	39003	80134	80134	80148	550640	80154	80256	140224	0	0	80007	0	0	100
80205	39003	80142	80142	80152	549608	80111	80212	140214	0	0	80005	0	0	100
80204	38977	80109	80109	80114	549807	80185	80285	140228	0	0	80004	0	0	100
80204	39009	80106	80106	80116	549968	80111	80212	140228	0	0	80006	0	0	100
80204	38975	80105	80105	80114	549062	80114	80216	140214	0	0	80004	0	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5561

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	39134	80033	80033	80044	547739	80020	80020	140020	80011	10
80025	38947	80060	80060	80076	547480	80020	80020	140020	80011	10
80024	38948	80021	80021	80020	547971	80020	80020	140020	80011	10
80024	38896	80021	80021	80020	550014	80020	80020	140020	80011	10
80024	38912	80021	80021	80020	548495	80020	80020	140020	80011	10
80024	38893	80021	80021	80020	551453	80020	80020	140020	80011	10
80024	38917	80021	80021	80020	549262	80020	80020	140020	80011	10
80024	38881	80021	80021	80020	545395	80020	80020	140020	80011	10
80024	38998	80021	80021	80020	548495	80020	80020	140020	80011	10
80024	38897	80021	80021	80020	552102	80020	80020	140020	80011	10

CCMP (immediate, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations