Icestorm: STR (pre-index, 32-bit) measurements

Code:

  str w0, [x6, #8]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1351	2059	1041	1018	1040	1000	4645	17749	2000	1000	2000	1001	1000
1004	1077	2001	1001	1000	1000	1000	4649	17695	2000	1000	2000	1001	1000
1004	1078	2001	1001	1000	1000	1000	4649	18181	2000	1000	2000	1001	1000
1004	1078	2001	1001	1000	1000	1000	4649	18595	2000	1000	2000	1001	1000
1004	1069	2001	1001	1000	1000	1000	4649	17659	2000	1000	2000	1001	1000
1004	1116	2001	1001	1000	1000	1000	4653	18361	2000	1000	2000	1001	1000
1004	1082	2001	1001	1000	1000	1000	4649	17749	2000	1000	2000	1001	1000
1004	1084	2001	1001	1000	1000	1000	4649	17749	2000	1000	2000	1001	1000
1004	1099	2001	1001	1000	1000	1000	4649	17623	2000	1000	2000	1001	1000
1004	1077	2001	1001	1000	1000	1000	4649	17641	2000	1000	2000	1001	1000

Test 2: Latency 2->2

Code:

  str w0, [x6, #8]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0139

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11238	20404	10314	10090	10314	10003	60816	171381	20109	200	10010	200	20020	10007	10000	100
10204	10109	20105	10105	10000	10106	10001	43546	171418	20105	200	10008	200	20016	10004	10000	100
10204	10119	20104	10104	10000	10104	10002	43551	171115	20106	200	10008	200	20016	10004	10000	100
10204	10121	20104	10104	10000	10104	10002	43550	171313	20106	200	10008	200	20016	10004	10000	100
10204	10109	20104	10104	10000	10104	10002	43550	171259	20106	200	10008	200	20016	10004	10000	100
10204	10442	20101	10101	10000	10100	10003	51404	171255	20109	200	10010	200	20016	10004	10000	100
10204	10087	20104	10104	10000	10104	10001	43509	171598	20105	200	10008	200	20016	10003	10000	100
10204	10118	20103	10103	10000	10104	10001	43520	171868	20105	200	10008	200	20016	10004	10000	100
10204	10167	20105	10105	10000	10106	10003	104590	171633	20109	200	10010	200	20020	10001	10000	100
10204	10138	20104	10104	10000	10104	10002	43514	171727	20106	200	10008	200	20016	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0148

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11284	20307	10217	10090	10218	10002	43012	172321	20016	20	10008	20	20000	10001	10000	10
10024	10155	20011	10011	10000	10010	10000	43071	171901	20010	20	10000	20	20000	10001	10000	10
10024	10148	20011	10011	10000	10010	10000	42995	171847	20010	20	10000	20	20000	10001	10000	10
10024	10146	20011	10011	10000	10010	10000	42995	171847	20010	20	10000	20	20000	10001	10000	10
10024	10145	20011	10011	10000	10010	10000	43071	171901	20010	20	10000	20	20000	10001	10000	10
10024	10145	20011	10011	10000	10010	10000	42995	171847	20010	20	10000	20	20000	10001	10000	10
10024	10148	20011	10011	10000	10010	10000	42995	171847	20010	20	10000	20	20000	10001	10000	10
10024	10149	20011	10011	10000	10010	10000	43071	171991	20010	20	10000	20	20000	10001	10000	10
10024	10148	20011	10011	10000	10010	10000	43071	171901	20010	20	10000	20	20000	10001	10000	10
10024	10142	20011	10011	10000	10010	10000	43071	171901	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  str w0, [x6, #8]!
  str w0, [x7, #8]!
  str w0, [x8, #8]!
  str w0, [x9, #8]!
  str w0, [x10, #8]!
  str w0, [x11, #8]!
  str w0, [x12, #8]!
  str w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	80968	160401	80311	80090	80311	80035	240419	1360781	160175	200	80048	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	80951	160305	80215	80090	80214	80002	240042	1360157	160016	20	80008	20	160096	80037	80000	10
80024	80053	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160096	80037	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10

STR (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations