Icestorm: TBNZ (not taken) measurements

Code:

  tbnz x0, #1, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	4942	3326	3326	4342	11613	3871	4452	1148	1
1004	631	1009	1009	1012	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1

Count: 8

Code:

  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4

Initialization

  mov x0, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5836

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	54626	84376	84376	86272	241287	80429	80610	80325	1	100
80205	46978	80289	80289	80364	240417	80139	80252	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100
80204	46686	80107	80107	80110	240330	80110	80212	80212	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5837

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	122622	119657	119657	136403	249075	83025	83772	82433	1	10
80024	47937	80761	80761	81094	241935	80645	80835	80158	1	10
80024	46806	80079	80079	80106	240237	80079	80101	80087	1	10
80024	46752	80045	80045	80054	240162	80054	80070	80070	1	10
80024	46751	80045	80045	80054	240162	80054	80072	80124	1	10
80024	46751	80045	80045	80054	240138	80046	80060	80060	1	10
80024	46742	80037	80037	80046	240309	80103	80119	80060	1	10
80024	46742	80037	80037	80046	240279	80093	80105	80060	1	10
80024	46742	80037	80037	80046	240138	80046	80060	80060	1	10
80024	46742	80037	80037	80046	240138	80046	80060	80060	1	10

TBNZ (not taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations