Icestorm: MOVN (32-bit) measurements

Code:

  movn w0, #0x1234, lsl 16
  nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 3 nops): 1.000

Issues: 0.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	map int uop (7c)	? int output thing (e9)	? int retires (ef)
4004	2035	1	1	1000	1	1000
4004	1060	1	1	1000	1	1000
4004	1025	1	1	1000	1	1000
4004	1025	1	1	1000	1	1000
4004	1025	1	1	1000	1	1000
4004	1025	1	1	1000	1	1000
4004	1025	1	1	1000	1	1000
4004	1025	1	1	1000	1	1000
4004	1025	1	1	1000	1	1000
4004	1025	1	1	1000	1	1000

Count: 8

Code:

  movn w0, #0x1234, lsl 16
  movn w1, #0x1234, lsl 16
  movn w2, #0x1234, lsl 16
  movn w3, #0x1234, lsl 16
  movn w4, #0x1234, lsl 16
  movn w5, #0x1234, lsl 16
  movn w6, #0x1234, lsl 16
  movn w7, #0x1234, lsl 16

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	20312	40010	40010	40013	120039	40013	80226	200	0	39910	0	0	80100
80204	20096	40010	40010	40013	120036	40012	80224	862	522	40254	285	1	80502
80204	20098	40010	40010	40013	120036	40012	80224	200	0	39909	0	0	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	0	39909	0	0	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	0	39909	0	0	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	0	39909	0	0	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	0	39909	0	0	80100
80204	20096	40010	40010	40013	120036	40012	80224	200	0	39909	0	0	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	0	39909	0	0	80100
80204	20086	40009	40009	40012	120036	40012	80224	200	0	39909	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	21950	40022	40022	40025	120052	40011	80020	20	40001	80010
80024	20150	40011	40011	40010	120045	40010	80020	20	40001	80010
80024	20065	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20123	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20079	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20054	40011	40011	40010	120049	40010	80020	20	40001	80010

MOVN (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations