Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (uxth, 32-bit)

Test 1: uops

Code:

  subs w0, w0, w1, uxth
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000

Test 2: Latency 1->2

Code:

  subs w0, w0, w1, uxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290011010410206202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205296101005810068200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010

Test 3: Latency 1->3

Code:

  subs w0, w1, w0, uxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290011010410206202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255291921002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs w0, w1, w2, uxth
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201057892332010520212302213000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057897202014320256302183000120100
20204300303010130101201057893692010520212302183000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157893782001520032300383000120010
20024300303001130011200157894382001020020300203000120010
20024300303001130011200107897922005020072300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs w0, w1, w2, uxth
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201057891712010620214302153000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157894592001520032300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010

Test 6: throughput

Count: 8

Code:

  subs w0, w8, w9, uxth
  subs w1, w8, w9, uxth
  subs w2, w8, w9, uxth
  subs w3, w8, w9, uxth
  subs w4, w8, w9, uxth
  subs w5, w8, w9, uxth
  subs w6, w8, w9, uxth
  subs w7, w8, w9, uxth
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
802045340416011416011480123109959680127802281602480160014080100
802045340416011416011480123110007680123802241602480160014080100
802045340416011416011480123110007680123802241602480160014080100
802045340416011416011480123110007680123802241602480160014080100
802045340416011416011480123110007680123802241602480160014080100
802045340416011416011480123110007680123802241602480160014080100
802045340416011416011480123110007680123802241602480160014080100
802045340416011416011480123110007680123802241602480160014080100
802045340416011416011480123110007680123802241602480160014080100
802045340416011416011480123110007680123802241602480160014080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002453379160037160037800441107842800488004816007616003280010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201106107801768017616002016001180010
8002453371160021160021800201107732800208002016002016001180010