Icestorm: STR (post-index, 32-bit) measurements

Code:

  str w0, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1269	2059	1041	1018	1040	1000	4641	18055	2000	1000	2000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4641	17497	2000	1000	2000	1001	1000
1004	1103	2001	1001	1000	1000	1000	4637	17587	2000	1000	2000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4641	17551	2000	1000	2000	1001	1000
1004	1106	2001	1001	1000	1000	1000	4621	17713	2000	1000	2000	1001	1000
1004	1101	2001	1001	1000	1000	1000	4641	18235	2000	1000	2000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4637	17659	2000	1000	2000	1001	1000
1004	1078	2001	1001	1000	1000	1000	4641	17659	2000	1000	2000	1001	1000
1004	1116	2001	1001	1000	1000	1000	4641	17641	2000	1000	2000	1001	1000
1004	1065	2001	1001	1000	1000	1000	4641	17587	2000	1000	2000	1001	1000

Test 2: Latency 2->2

Code:

  str w0, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0232

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11197	20400	10310	10090	10310	10003	57874	171934	20109	200	10010	200	20020	10005	10000	100
10204	10150	20104	10104	10000	10104	10002	43554	171925	20106	200	10008	200	20016	10004	10000	100
10204	10149	20104	10104	10000	10104	10002	43554	171925	20106	200	10008	200	20016	10004	10000	100
10204	10149	20104	10104	10000	10104	10002	43554	171925	20106	200	10008	200	20016	10004	10000	100
10204	10149	20104	10104	10000	10104	10036	46158	173181	20179	202	10049	200	20016	10004	10000	100
10204	10149	20104	10104	10000	10104	10002	43554	171925	20106	200	10008	200	20016	10004	10000	100
10204	10149	20104	10104	10000	10104	10002	43541	172177	20106	200	10008	200	20016	10004	10000	100
10204	10163	20104	10104	10000	10104	10002	43549	172397	20106	200	10008	200	20016	10004	10000	100
10204	10164	20104	10104	10000	10104	10002	43559	172541	20106	200	10008	200	20016	10004	10000	100
10204	10310	20103	10103	10000	10104	10003	55906	174472	20109	200	10010	200	20020	10005	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0104

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11158	20304	10214	10090	10214	10038	75278	172827	20092	20	10048	20	20000	10001	10000	10
10024	10087	20011	10011	10000	10010	10036	95561	172191	20086	20	10040	20	20000	10001	10000	10
10025	10178	20063	10046	10017	10050	10072	99605	174101	20162	20	10080	20	20000	10001	10000	10
10024	10102	20011	10011	10000	10010	10000	42958	170893	20010	20	10000	20	20000	10001	10000	10
10024	10102	20011	10011	10000	10010	10000	42958	170893	20010	20	10000	20	20000	10001	10000	10
10024	10102	20011	10011	10000	10010	10000	42958	170911	20010	20	10000	20	20000	10001	10000	10
10024	10092	20011	10011	10000	10010	10000	42958	171073	20010	20	10000	20	20000	10001	10000	10
10024	10102	20011	10011	10000	10010	10000	42958	171073	20010	20	10000	20	20000	10001	10000	10
10024	10092	20011	10011	10000	10010	10000	42958	170911	20010	20	10000	20	20000	10001	10000	10
10024	10092	20011	10011	10000	10010	10000	42958	170893	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  str w0, [x6], #8
  str w0, [x7], #8
  str w0, [x8], #8
  str w0, [x9], #8
  str w0, [x10], #8
  str w0, [x11], #8
  str w0, [x12], #8
  str w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	80839	160401	80311	80090	80311	80002	240312	1360157	160106	200	80008	200	160096	80045	80000	100
80204	80053	160105	80105	80000	80104	80074	240552	1364700	160258	200	80088	200	160176	80085	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160096	80045	80000	100
80204	80140	160163	80145	80018	80144	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80914	160453	80345	80108	80344	80110	240672	1364371	160334	200	80128	200	160096	80045	80000	100
80204	80045	160105	80105	80000	80104	80075	240558	1362557	160261	200	80090	200	160096	80045	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1360141	160106	200	80008	200	160096	80045	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	81010	160305	80215	80090	80214	80038	240162	1361784	160092	20	80048	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80036	240155	1360669	160088	20	80050	20	160080	80041	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1360027	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80036	240150	1362187	160086	20	80040	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80036	240150	1361071	160086	20	80040	20	160336	80157	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1360063	160010	20	80000	20	160000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160160	80081	80000	10
80024	80045	160011	80011	80000	80010	80035	240149	1360683	160085	20	80048	20	160160	80081	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10

STR (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations