Icestorm: LDURSH (32-bit) measurements

Code:

  ldursh w0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	805	1031	1	1030	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	552	1001	1	1000	1000	8328	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8742	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8256	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8238	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursh w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70154	40108	30107	10001	30130	10003	1859539	693993	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859716	694113	40106	30212	10004	60224	10004	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859662	694093	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40205	70079	40111	30109	10002	30135	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70153	40018	30017	10001	30040	10055	1866149	697034	40200	30184	10056	60020	10000	30003	10000	30010
40024	70144	40025	30022	10003	30043	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70048	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010

Test 3: throughput

Count: 8

Code:

  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40187	80125	101	80024	100	80008	300	280064	80108	200	80012	200	80012	1	80000	100
80205	40096	80135	101	80034	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40207	80037	11	80026	10	80000	30	620388	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640130	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80069	1	80000	10
80024	40115	80011	11	80000	10	80010	30	241646	80020	20	80014	20	80012	1	80000	10
80024	40055	80015	11	80004	10	80008	30	640142	80018	20	80012	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10

LDURSH (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations