Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDURSH (32-bit)

Test 1: uops

Code:

  ldursh w0, [x6, #1]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10058051031110301000823810001000100011000
10045541001110001000823810001000100011000
10045471001110001000823810001000100011000
10045471001110001000823810001000100011000
10045521001110001000832810001000100011000
10045471001110001000874210001000100011000
10045471001110001000823810001000100011000
10045471001110001000823810001000100011000
10045471001110001000825610001000100011000
10045471001110001000823810001000100011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursh w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570154401083010710001301301000318595396939934010630212100046022410004300031000030100
4020470049401033010310000301031000318597166941134010630212100046022410004300031000030100
4020470050401033010310000301031000318596626940934010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020570079401113010910002301351000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100
4020470049401033010310000301031000318596356940834010630212100046022410004300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570153400183001710001300401005518661496970344020030184100566002010000300031000030010
4002470144400253002210003300431000018596526947144001030020100006002010000300031000030010
4002470049400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470048400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002010000300031000030010

Test 3: throughput

Count: 8

Code:

  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  ldursh w0, [x6, #1]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540187801251018002410080008300280064801082008001220080012180000100
8020540096801351018003410080008300640070801082008001220080012180000100
8020440045801011018000010080008300640070801082008001220080012180000100
8020440045801011018000010080008300640070801082008001220080012180000100
8020440045801011018000010080008300640070801082008001220080012180000100
8020440045801011018000010080008300640070801082008001220080012180000100
8020440045801011018000010080008300640070801082008001220080012180000100
8020440045801011018000010080008300640070801082008001220080012180000100
8020440045801011018000010080008300640070801082008001220080012180000100
8020440045801011018000010080008300640070801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540207800371180026108000030620388800102080000208000018000010
8002440054800111180000108000030640130800102080000208000018000010
8002440043800111180000108000030640040800102080000208000018000010
8002440043800111180000108000030640040800102080000208000018000010
8002440051800111180000108000030640040800102080000208000018000010
8002440043800111180000108000030640040800102080000208006918000010
8002440115800111180000108001030241646800202080014208001218000010
8002440055800151180004108000830640142800182080012208000018000010
8002440047800111180000108000030640112800102080000208000018000010
8002440047800111180000108000030640112800102080000208000018000010