Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MVN (register, asr, 32-bit)

Test 1: uops

Code:

  mvn w0, w0, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000

Test 2: Latency 1->2

Code:

  mvn w0, w0, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045291861010410212102102000110100
10204200302010120101101045291861010410212102102000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045291861010410212102122000110100
10204200302010120101101045295081013910254102122000110100
10204200302010120101101045291861010410212102122000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1002420030200212002110025052914600100251003400100202001110010
1002420030200212002110020052925300100201002000100722002510010
1002420030200212002110020052925300100201002000100202001110010
1002420030200212002110020052925300100201002000100202001110010
1002420030200212002110020052925300100201002000100202001110010
1002420030200212002110020052925300100201002000100202001110010
1002420030200212002110020052925300100201002000100202001110010
1002420030200212002110020052925300100201002000100202001110010
1002420030200212002110020052925300100201002000100202001110010
1002420030200212002110020052925300100201002000100202001110010

Test 3: throughput

Count: 8

Code:

  mvn w0, w8, asr #17
  mvn w1, w8, asr #17
  mvn w2, w8, asr #17
  mvn w3, w8, asr #17
  mvn w4, w8, asr #17
  mvn w5, w8, asr #17
  mvn w6, w8, asr #17
  mvn w7, w8, asr #17
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204534151601161601160080129001360566008013080236008023616001780100
80204534151601161601160080130001360838008013080236008023416001780100
80204534041601171601170080130001360838008013080236008023616001780100
80204534041601171601170080130001360838008013080236008023616001780100
80204534041601171601170080130001360838008013080236008023616001780100
80204534041601171601170080130001360838008013080236008023616001780100
80205534351601621601620080177001360838008013080236008028716005980100
80204534041601171601170080130001360838008013080236008023616001780100
80204534041601171601170080130001360838008013080236008023616001780100
80204534041601171601170080130001360838008013080236008023616001780100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800245339016003916003980051135997580051800568002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020135990380020800208002016001180010
800255340716008116008180096135964680020800208002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337816003916003980051135990380020800208002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020136018080071800718002016001180010
800245337116002116002180020136114080246802648015916011480010
800245338316002116002180020135990380020800208002016001180010