Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (uxtb, 32-bit)

Test 1: uops

Code:

  cmn w0, w1, uxtb
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn w0, w1, uxtb
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
202043003030101301012010578923120105202103021500300010010100
202043003030101301012010578936920105202123021800300010010100
202043003030101301012010578936920105202123021800300010010100
202043003030101301012010578936920105202123021800300010010100
202043003030101301012010578936920105202123021800300010010100
202043003030101301012010578936920105202123021800300010010100
202043003030101301012010578936920105202123021800300010010100
202043003030101301012010578936920105202123021800300010010100
202043003030101301012010578936920105202123021800300010010100
202043003030101301012010578936920105202123021800300010010100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200167894012001520030300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107898042005120076301043001510010
20024300303001130011200157893602001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn w0, w1, uxtb
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201067892472010820214302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201067892312010520210302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894592001520032300203000110010
20024300303001130011200107894382001020020300203000110010

Test 4: throughput

Count: 8

Code:

  cmn w0, w1, uxtb
  cmn w0, w1, uxtb
  cmn w0, w1, uxtb
  cmn w0, w1, uxtb
  cmn w0, w1, uxtb
  cmn w0, w1, uxtb
  cmn w0, w1, uxtb
  cmn w0, w1, uxtb
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
8020453404160117160117801270117760100801308023000160252016001600100
8020453402160114160114801230117760300801238022400160248016001400100
8020453402160114160114801230117762700801238022400160248016001400100
8020453402160114160114801230117760700801238022400160248016001400100
8020453402160114160114801230117761900801238022400160248016001400100
8020453402160114160114801230117760300801238022400160248016001400100
8020453402160114160114801230117762700801238022400160248016001400100
8020453402160114160114801230117760300801238022400160248016001400100
8020453402160114160114801230117762700801238022400160328016006200100
8020453402160114160114801230117762300801238022400160248016001400100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002453405160039160039800471171972800208002016002016001110
8002453371160021160021800201171999800208002016002016001110
8002453371160021160021800201171999800208002016002016001110
8002453371160021160021800201171999800208002016002016001110
8002453371160021160021800201171999800208002016002016001110
8002453371160021160021800201171999800208002016002016001110
8002453371160021160021800201171999800208002016015816007410
8002453371160021160021800201171999800208002016002016001110
8002453371160021160021800201171999800208002016002016001110
8002453371160021160021800201171999800208002016002016001110