Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSH (32-bit)

Test 1: uops

Code:

  ldrsh w0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1129	1031	1	1030	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	546	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8166	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70151	40108	30107	10001	30130	10003	1859539	693993	40106	30212	10004	60302	10017	30009	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10015	1862734	695327	40150	30251	10017	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1861417	694809	40106	30212	10004	60224	10004	30002	10000	30100
40204	70049	40102	30102	10000	30103	10003	1859554	694057	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10015	1860142	694263	40150	30247	10017	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40025	70172	40018	30017	10001	30040	10000	1859604	694669	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70049	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	0	30003	10000	0	30010

Test 3: throughput

Count: 8

Code:

  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40193	80125	101	0	80024	100	0	80008	300	256064	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	0	80000	100	0	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	0	80000	100	0	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	0	80000	100	0	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	0	80000	100	0	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	0	80000	100	0	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	0	80000	100	0	80008	300	641384	80108	200	80012	200	80068	1	80000	100
80204	40048	80101	101	0	80000	100	0	80200	300	416954	80300	200	80240	200	80012	1	80000	100
80204	40064	80101	101	0	80000	100	0	80105	307	615815	80207	202	80125	200	80012	1	80000	100
80204	40045	80101	101	0	80000	100	0	80008	300	640070	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40218	80037	11	80026	10	80008	30	400190	80018	20	80012	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80025	40100	80041	11	80030	10	80000	30	640328	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640256	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640202	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10