Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLDL3STRM)

Test 1: uops

Code:

  prfm pldl3strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2149	1001	1	1000	1000	35142	1000	1000	1000	1	1000
1004	2123	1001	1	1000	1000	35606	1000	1000	1000	1	1000
1004	2074	1001	1	1000	1000	35158	1000	1000	1000	1	1000
1004	2123	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pldl3strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0026

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20897	20102	10102	10000	10106	10000	60362	355153	20101	10203	10003	10204	10004	10001	10000	10100
20204	20384	20101	10101	10000	10101	10000	60407	355173	20102	10204	10004	10204	10004	10001	10000	10100
20204	20384	20101	10101	10000	10102	10000	60407	355173	20102	10204	10004	10204	10004	10001	10000	10100
20204	20237	20101	10101	10000	10102	10000	60407	355173	20102	10204	10004	10206	10006	10002	10000	10100
20204	20188	20101	10101	10000	10102	10000	60319	354363	20102	10204	10004	10204	10004	10001	10000	10100
20204	20229	20101	10101	10000	10102	10006	61037	353629	20118	10214	10014	10204	10004	10001	10000	10100
20204	20384	20101	10101	10000	10102	10000	60407	355173	20102	10204	10004	10204	10004	10001	10000	10100
20204	20376	20101	10101	10000	10102	10000	60407	355173	20102	10204	10004	10204	10004	10001	10000	10100
20204	20345	20103	10103	10000	10108	10008	60757	350951	20121	10213	10014	10211	10011	10006	10000	10100
20204	20077	20106	10106	10000	10109	10004	61694	347659	20114	10212	10012	10212	10012	10005	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0240

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	21156	20011	10011	10000	10013	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010
20024	20240	20011	10011	10000	10010	10000	60820	352731	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pldl3strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0818

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20889	10101	101	10000	100	10000	300	363866	10100	200	10008	200	10012	1	10000	100
10204	20901	10101	101	10000	100	10000	300	360326	10100	200	10008	200	10008	1	10000	100
10204	20663	10101	101	10000	100	10000	300	359274	10100	200	10004	200	10008	1	10000	100
10204	21017	10195	105	10090	104	10000	300	360416	10100	200	10008	200	10012	1	10000	100
10204	20719	10101	101	10000	100	10006	300	358574	10106	200	10012	200	10004	1	10000	100
10205	20933	10163	103	10060	102	10000	300	363944	10100	200	10008	200	10004	1	10000	100
10204	21034	10131	101	10030	100	10000	300	363598	10100	200	10008	200	10008	1	10000	100
10204	20828	10101	101	10000	100	10098	310	367916	10201	204	10120	200	10004	1	10000	100
10204	20862	10101	101	10000	100	10000	300	364956	10100	200	10004	200	10012	1	10000	100
10204	20908	10101	101	10000	100	10000	300	363550	10100	200	10004	200	10008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0048

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20047	10011	11	10000	10	10000	30	349210	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349424	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10