Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (shifted immediate, 32-bit)

Test 1: uops

Code:

  adds w0, w0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000
100410301001100110002504310001000100010011000

Test 2: Latency 1->2

Code:

  adds w0, w0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082514651010910210102081000110100
10204100301010110101101072516631010710208102081000110100
10204100301010110101101082517741010810208102081000110100
10204100301010110101101082517741010810208102081000110100
10204100301010110101101082517741010810208102081000110100
10204100301010110101101082517741010810208102081000110100
10204100301010110101101082517741010810208102081000110100
10204100301010110101101082517741010810208102081000110100
10204100301010110101101082517741010810208102081000110100
10204100301010110101101082517741010810208102081000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010
10024100301002110021100202531611002010020100201001110010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  adds w0, w1, #3, lsl #12
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302010120101201075194162010720212202162000120100
20204200302010120101201075195482010820216202162000120100
20204200302010120101201085195482010820216202162000120100
20204200302010120101201085195482010820216202162000120100
20204200302010120101201085195482010820216202162000120100
20204200302010120101201085195482010820216202162000120100
20204200302010120101201085195482010820216202162000120100
20204200302010120101201085195482010820216202162000120100
20204200302010120101201085195482010820216202162000120100
20204200302010120101201085195482010820216202162000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302001120011200185196382001820036200202000120010
20024200302001120011200105195982001020020200202000120010
20024200302001120011200105195982001020020200202000120010
20024200302001120011200105195982001020020200202000120010
20024200302001120011200105195982001020020200202000120010
20024200302001120011200105195982001020020200202000120010
20024200302001120011200105195982001020020200202000120010
20024200302001120011200105195982001020020200202000120010
20024200302001120011200105199562005820080200202000120010
20024200302001120011200105195982001020020200202000120010

Test 4: throughput

Count: 8

Code:

  adds w0, w8, #3, lsl #12
  adds w1, w8, #3, lsl #12
  adds w2, w8, #3, lsl #12
  adds w3, w8, #3, lsl #12
  adds w4, w8, #3, lsl #12
  adds w5, w8, #3, lsl #12
  adds w6, w8, #3, lsl #12
  adds w7, w8, #3, lsl #12
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204401058011080110801132403458011580216802168001280100
80204400818011280112801152403458011580216802168001280100
80205401068014180141801482403458011580216802168001280100
80204400818011280112801152403458011580216802168001280100
80204400818011280112801152403458011580216802168001280100
80204400818011280112801152403458011580216802168001280100
80204400818011280112801152403458011580216802168001280100
80204400818011280112801152403458011580216802168001280100
80204400818011280112801152403458011580216802168001280100
80204400818011280112801152403458011580216802168001280100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024400888003280032800352400658002080020800208001180010
80024400358002180021800202400658002080020800208001180010
80025400618005980059800662400658002080020800208001180010
80024400308002180021800202400658002080020800208001180010
80024400308002180021800202401318003780038800208001180010
80024400308002180021800202400658002080020800208001180010
80024400308002180021800202400658002080020800208001180010
80024400308002180021800202400658002080020800208001180010
80024400308002180021800202400658002080020800208001180010
80024400308002180021800202400658002080020800208001180010