Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
strb w0, [x6, #8]
mov x0, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
1005 | 1149 | 1019 | 1 | 1018 | 1000 | 17043 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1047 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1039 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1039 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1039 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1039 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1039 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1039 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1039 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 1039 | 1001 | 1 | 1000 | 1000 | 16883 | 1000 | 1000 | 2000 | 1 | 1000 |
Count: 8
Code:
strb w0, [x6, #8] strb w0, [x6, #8] strb w0, [x6, #8] strb w0, [x6, #8] strb w0, [x6, #8] strb w0, [x6, #8] strb w0, [x6, #8] strb w0, [x6, #8]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
80205 | 80540 | 80191 | 101 | 80090 | 100 | 80001 | 300 | 1359974 | 80101 | 200 | 80008 | 200 | 160016 | 1 | 80000 | 100 |
80204 | 80047 | 80101 | 101 | 80000 | 100 | 80001 | 300 | 1359886 | 80101 | 200 | 80008 | 200 | 160016 | 1 | 80000 | 100 |
80204 | 80039 | 80101 | 101 | 80000 | 100 | 80001 | 300 | 1359886 | 80101 | 200 | 80008 | 200 | 160016 | 1 | 80000 | 100 |
80204 | 80039 | 80101 | 101 | 80000 | 100 | 80001 | 300 | 1359886 | 80101 | 200 | 80008 | 200 | 160344 | 1 | 80000 | 100 |
80204 | 80039 | 80101 | 101 | 80000 | 100 | 80001 | 300 | 1359886 | 80101 | 200 | 80008 | 200 | 160016 | 1 | 80000 | 100 |
80205 | 80067 | 80118 | 101 | 80017 | 100 | 80001 | 300 | 1359886 | 80101 | 200 | 80008 | 200 | 160016 | 1 | 80000 | 100 |
80204 | 80039 | 80101 | 101 | 80000 | 100 | 80145 | 300 | 1364206 | 80245 | 200 | 80172 | 200 | 160016 | 1 | 80000 | 100 |
80204 | 80039 | 80101 | 101 | 80000 | 100 | 80001 | 300 | 1359886 | 80101 | 200 | 80008 | 200 | 160016 | 1 | 80000 | 100 |
80204 | 80039 | 80101 | 101 | 80000 | 100 | 80001 | 300 | 1359886 | 80101 | 200 | 80008 | 200 | 160016 | 1 | 80000 | 100 |
80204 | 80039 | 80101 | 101 | 80000 | 100 | 80001 | 300 | 1359886 | 80101 | 200 | 80008 | 200 | 160016 | 1 | 80000 | 100 |
Result (median cycles for code divided by count): 1.0006
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
80025 | 80151 | 80029 | 11 | 80018 | 10 | 80037 | 30 | 1360292 | 80047 | 20 | 80052 | 20 | 160016 | 1 | 80000 | 10 |
80024 | 80045 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 1360007 | 80010 | 20 | 80000 | 20 | 160104 | 1 | 80000 | 10 |
80024 | 80045 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 1360007 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 80000 | 10 |
80024 | 80045 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 1360007 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 80000 | 10 |
80024 | 80045 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 1360007 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 80000 | 10 |
80024 | 80045 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 1360007 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 80000 | 10 |
80024 | 80045 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 1360115 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 80000 | 10 |
80025 | 80119 | 80028 | 11 | 80017 | 10 | 80000 | 30 | 1360007 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 80000 | 10 |
80024 | 80045 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 1360007 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 80000 | 10 |
80024 | 80045 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 1360007 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 80000 | 10 |