Icestorm: CSINC (64-bit) measurements

Code:

  csinc x0, x0, x1, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25898	1040	1048	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	3000	1001	1000

Test 2: Latency 1->2

Code:

  csinc x0, x0, x1, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	259425	10108	10216	30242	10001	10100
10204	10030	10101	10101	10107	259311	10107	10214	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259474	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10025	10060	10035	10035	10069	259591	10020	10020	30020	10011	10010

Test 3: Latency 1->3

Code:

  csinc x0, x1, x0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	259329	10107	10214	30242	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	30236	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259528	10030	10038	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	30020	10011	10010

Test 4: Latency 1->4

Chain cycles: 1

Code:

  csinc x0, x1, x2, hi
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20208	519319	20209	20216	40232	20101	10100
20204	20030	20201	20201	20208	519299	20211	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40328	20115	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100
20204	20030	20201	20201	20208	520861	20340	20352	40232	20101	10100
20204	20030	20201	20201	20208	519448	20208	20216	40232	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20028	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	519591	20020	20020	40020	20011	10010

Test 5: throughput

Count: 8

Code:

  csinc x0, x8, x9, hi
  csinc x1, x8, x9, hi
  csinc x2, x8, x9, hi
  csinc x3, x8, x9, hi
  csinc x4, x8, x9, hi
  csinc x5, x8, x9, hi
  csinc x6, x8, x9, hi
  csinc x7, x8, x9, hi

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26854	80115	80115	80120	290032	80120	80222	240266	80015	80100
80204	26740	80114	80114	80119	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	292702	80120	80222	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	240272	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	28072	80038	80038	80052	309563	80049	80050	240020	80011	80010
80024	26778	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26728	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26723	80021	80021	80020	333214	80108	80114	240020	80011	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26729	80021	80021	80020	426780	80020	80020	240020	80011	80010
80024	26723	80021	80021	80020	426780	80020	80020	240020	80011	80010

CSINC (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations