Icestorm: STR (unsigned offset, 64-bit) measurements

Code:

  str x0, [x6, #8]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1156	1019	1	1018	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000

Count: 8

Code:

  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]
  str x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80154	80119	101	0	80018	100	0	80001	300	1359974	0	80101	200	80008	0	200	160016	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	0	80101	200	80008	0	200	160016	1	80000	100
80204	80047	80101	101	0	80000	100	0	80037	300	1360562	0	80137	200	80052	0	200	160016	1	80000	100
80204	80050	80101	101	0	80000	100	0	80001	300	1360046	0	80101	200	80008	0	200	160016	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	0	80101	200	80008	0	200	160016	1	80000	100
80204	80047	80101	101	0	80000	100	0	80037	300	1360168	0	80137	200	80052	0	200	160016	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	0	80101	200	80008	0	200	160016	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	0	80101	200	80008	0	200	160016	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	0	80101	200	80008	0	200	160016	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	0	80101	200	80008	0	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	80148	80029	11	80018	10	80001	30	1360010	80011	20	80008	20	160016	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	0	10
80024	80047	80011	11	80000	10	80037	30	1360310	80047	20	80052	20	160000	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	0	10

STR (unsigned offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations