Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (OSH)

Test 1: uops

Code:

  dsb osh

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	16033	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16033	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000

Test 2: throughput

Code:

  dsb osh

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 16.0028

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	160033	10105	101	10004	100	10006	300	40024	0	10106	200	10006	0	200	1	10000	100
10204	160033	10107	101	10006	100	10004	300	40016	0	10104	200	10004	0	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	0	10104	200	10004	0	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	0	10104	200	10004	0	200	1	10000	100
10204	160028	10105	101	10004	100	11257	54068	58575	445	13583	3265	11477	13	200	1	9999	100
10204	160028	10107	101	10006	100	10006	300	40024	0	10106	200	10006	0	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	0	10104	200	10004	0	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	0	10104	200	10004	0	200	1	10000	100
10204	160028	10105	101	10004	100	10004	300	40016	0	10104	200	10004	0	200	1	10000	100
10204	160028	10105	101	10004	100	10014	300	40056	0	10114	200	10014	0	200	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 16.0028

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	160033	10015	11	10004	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160033	10011	11	10000	10	10030	30	40232	10040	20	10030	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10014	30	40364	10024	20	10014	20	1	9999	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10