Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PACDZB

Test 1: uops

Code:

  pacdzb x0
  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)? int output thing (e9)? int retires (ef)
1004602910011001100052725100010011000
1004602910011001100052725100010011000
1004602910011001100052725100010011000
1004602910011001100052725100010011000
1004602910011001100052725100010011000
1004602910011001100052725100010011000
1004602910011001100052725100010011000
1004602910011001100052725100010011000
1004602910011001100052725100010011000
1004602910011001100052725100010011000

Test 2: Latency 1->1

Code:

  pacdzb x0
  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1020460029102011020110200530325102002002001010110100
1020460029102011020110200530325102002002001010110100
1020460029102011020110200530325102002002001010110100
1020460029102011020110200530325102002002001010110100
1020460029102011020110200530325102002002001010410100
1020460029102011020110200530325102002002001010110100
1020460029102011020110200530325102002002001010110100
1020460029102011020110200530325102002002001010110100
1020460029102011020110200530325102002002001010110100
1020460029102011020110200530325102002002001010110100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024600291002110021100205298851003120201001110010
10024600291002110021100205297851002020201001110010
10024600291002110021100205297851002020201001110010
10024600291002110021100205297851002020201001110010
10024600291002110021100205297851002020201001110010
10024600291002110021100205297851002020201001110010
10024600291002110021100205297851002020201001110010
10024600291002110021100205297851002020201001110010
10024600291002110021100205298851003120201001110010
10025600581002410024100315297851002020201001110010

Test 3: throughput

Count: 8

Code:

  pacdzb x0
  pacdzb x1
  pacdzb x2
  pacdzb x3
  pacdzb x4
  pacdzb x5
  pacdzb x6
  pacdzb x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802041600308020180201802021360529802202002008010180100
802041600308020180201802021360430802022002008010180100
802041600308020180201802021360481802022002008010180100
802041600308020180201802021360481802022002008010180100
802041600308020180201802021360481802022002008010180100
802041600308020180201802021360481802022002008010180100
802041600308020180201802021360481802022002008010180100
802041600758021380213802201361009802762002008011480100
802041604398026480264802961360481802022002008010180100
802041600308020180201802021360481802022002008010180100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024160030800218002108002213598908002220208001180010
80024160030800218002108002013599318002020208002480010
80024160030800218002108002013605618009820208001180010
80024160030800218002108002013599318002020208001180010
80024160030800218002108002013599318002020208001180010
80024160030800218002108002013599318002020208001180010
80025160064800318003108004013599318002020208001180010
80024160030800218002108002013599318002020208001180010
80024160030800218002108002013599318002020208001180010
80024160030800218002108002013599318002020208002080010