Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (ISHST)

Test 1: uops

Code:

  dsb ishst

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	16033	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16033	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	999
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000
1004	16028	1001	1	1000	1000	4000	1000	1000	1	1000

Test 2: throughput

Code:

  dsb ishst

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 16.0028

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	160058	10115	101	0	10014	100	0	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160033	10105	101	0	10004	100	0	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	0	10004	100	0	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160043	10113	101	0	10012	100	0	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	0	10004	100	0	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	0	10004	100	0	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	0	10004	100	0	10004	300	40016	10104	200	10004	200	1	9999	100
10204	160028	10105	101	0	10004	100	0	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	0	10004	100	0	10004	300	40016	10104	200	10004	200	1	10000	100
10204	160028	10105	101	0	10004	100	0	10004	300	40016	10104	200	10004	200	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 16.0028

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	160045	10023	11	10012	10	10004	30	40016	10014	20	10004	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160050	10025	11	10014	10	10016	30	40058	10026	20	10016	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160028	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160052	10027	11	10016	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160033	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10
10024	160033	10011	11	10000	10	10000	30	40000	10010	20	10000	20	1	10000	10