Icestorm: LDR (unsigned offset, 64-bit) measurements

Code:

  ldr x0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	700	1027	1	1026	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70154	40108	30107	10001	30130	10003	1859539	693993	40106	30212	10004	60224	10004	30003	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30001	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70127	40102	30102	10000	30103	10003	1859635	694090	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70158	40018	30017	10001	30040	10003	1859590	694710	40016	30032	10004	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40167	80129	101	80028	100	80008	300	280190	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80059	300	282499	80159	200	80072	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640358	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	280190	80108	200	80012	200	80012	1	80000	100
80204	40058	80105	101	80004	100	80008	300	480190	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40250	80039	11	80028	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80048	30	640676	80058	20	80057	20	80000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640094	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40132	80011	11	80000	10	80000	30	640328	80010	20	80000	20	80000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10

LDR (unsigned offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations