Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (unsigned offset, 64-bit)

Test 1: uops

Code:

  ldr x0, [x6, #8]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10057001027110261000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000
10045541001110001000823810001000100011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570154401083010710001301301000318595396939934010630212100046022410004300031000030100
4020470042401023010210000301031000318594466940134010630212100046022410004300011000030100
4020470042401023010210000301031000318594466940134010630212100046022410004300021000030100
4020470042401023010210000301031000318594466940134010630212100046022410004300021000030100
4020470127401023010210000301031000318596356940904010630212100046022410004300021000030100
4020470042401023010210000301031000318594466940134010630212100046022410004300021000030100
4020470042401023010210000301031000318594466940134010630212100046022410004300021000030100
4020470042401023010210000301031000318594466940134010630212100046022410004300021000030100
4020470042401023010210000301031000318594466940134010630212100046022410004300021000030100
4020470042401023010210000301031000318594466940134010630212100046022410004300021000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570158400183001710001300401000318595906947104001630032100046002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  ldr x0, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540167801291018002810080008300280190801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080059300282499801592008007220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640196801082008001220080012180000100
8020440052801011018000010080008300640358801082008001220080012180000100
8020440052801011018000010080008300280190801082008001220080012180000100
8020440058801051018000410080008300480190801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540250800391180028108000030640040800102080000208000018000010
8002440043800111180000108000030640040800102080000208000018000010
8002440043800111180000108004830640676800582080057208000018000010
8002440046800111180000108000030640094800102080000208000018000010
8002440043800111180000108000030640040800102080000208000018000010
8002440132800111180000108000030640328800102080000208000018000010
8002440056800111180000108000030640040800102080000208000018000010
8002440043800111180000108000030640040800102080000208000018000010
8002440043800111180000108000030640040800102080000208000018000010
8002440043800111180000108000030640040800102080000208000018000010