Icestorm: CMN (shifted immediate, 64-bit) measurements

Code:

  cmn x0, #3, lsl #12

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	501	1001	1001	1000	3000	1000	1000	1000	1001
1004	396	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	395	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	388	1001	1001	1000	3000	1000	1000	1000	1001
1004	393	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	390	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  cmn x0, #3, lsl #12
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	0	519442	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519956	20058	20080	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010

Test 3: throughput

Count: 8

Code:

  cmn x0, #3, lsl #12
  cmn x0, #3, lsl #12
  cmn x0, #3, lsl #12
  cmn x0, #3, lsl #12
  cmn x0, #3, lsl #12
  cmn x0, #3, lsl #12
  cmn x0, #3, lsl #12
  cmn x0, #3, lsl #12

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3634

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29176	80114	80114	80118	240354	80118	80220	80220	80015	100
80204	29030	80114	80114	80118	240354	80118	80220	80220	80015	100
80204	29067	80113	80113	80118	240357	80119	80220	80220	80013	100
80204	29035	80115	80115	80119	240360	80120	80220	80220	80013	100
80204	29113	80114	80114	80119	240351	80117	80220	80220	80013	100
80204	29086	80112	80112	80116	240354	80118	80220	80220	80015	100
80204	29060	80115	80115	80120	240354	80118	80220	80220	80013	100
80204	29040	80115	80115	80120	240354	80118	80220	80216	80012	100
80204	29123	80113	80113	80118	240351	80117	80220	80220	80013	100
80204	29117	80113	80113	80118	240354	80118	80220	80220	80015	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30115	80034	80034	80038	240125	80039	80042	80020	80011	10
80024	29092	80021	80021	80020	240089	80020	80020	80020	80011	10
80024	29052	80021	80021	80020	240062	80020	80020	80020	80011	10
80024	28980	80021	80021	80020	240071	80020	80020	80020	80011	10
80024	28949	80021	80021	80020	240068	80020	80020	80020	80011	10
80024	29099	80021	80021	80020	240071	80020	80020	80020	80011	10
80024	29065	80021	80021	80020	240067	80020	80020	80020	80011	10
80024	28980	80021	80021	80020	240070	80020	80020	80020	80011	10
80024	28941	80021	80021	80020	240085	80020	80020	80020	80011	10
80024	29117	80021	80021	80020	240071	80020	80020	80020	80011	10

CMN (shifted immediate, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations