Icestorm: LDRB (pre-index) measurements

Code:

  ldrb w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1291	2040	1021	1019	1042	1000	20692	17571	2000	1000	1000	1000	1000	1001	1000	1000
2004	1093	2001	1001	1000	1000	1000	20840	17535	2000	1000	1000	1000	1000	1001	1000	1000
2004	1070	2001	1001	1000	1000	1000	20647	17811	2000	1000	1000	1000	1000	1001	1000	1000
2004	1081	2001	1001	1000	1000	1000	20968	17478	2000	1000	1000	1000	1000	1001	1000	1000
2004	1068	2001	1001	1000	1000	1000	21008	17434	2000	1000	1000	1000	1000	1001	1000	1000
2004	1081	2001	1001	1000	1000	1000	21323	17705	2000	1000	1000	1000	1000	1001	1000	1000
2004	1121	2001	1001	1000	1000	1000	21336	17665	2000	1000	1000	1000	1000	1001	1000	1000
2004	1083	2001	1001	1000	1000	1000	21108	17441	2000	1000	1000	1000	1000	1001	1000	1000
2004	1099	2001	1001	1000	1000	1000	21284	17714	2000	1000	1000	1000	1000	1001	1000	1000
2004	1108	2001	1001	1000	1000	1000	20417	18031	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0145

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71225	50161	40156	10005	40247	10012	1852330	536864	50152	40251	10013	70221	10003	40010	10000	40100
50204	70165	50109	40109	10000	40106	10003	1851603	535153	50109	40212	10004	70221	10004	40008	10000	40100
50204	70161	50109	40109	10000	40106	10003	1851657	535170	50109	40212	10004	70221	10004	40008	10000	40100
50204	70162	50109	40109	10000	40106	10003	1851657	535171	50109	40212	10004	70221	10004	40008	10000	40100
50204	70156	50109	40109	10000	40106	10003	1851981	535277	50109	40212	10004	70221	10004	40008	10000	40100
50204	70179	50109	40109	10000	40106	10003	1851630	535160	50109	40212	10004	70221	10004	40008	10000	40100
50204	70145	50109	40109	10000	40106	10003	1851225	535027	50109	40212	10004	70221	10004	40008	10000	40100
50204	70145	50109	40109	10000	40106	10013	1854339	535952	50155	40254	10014	70221	10004	40008	10000	40100
50204	70145	50109	40109	10000	40106	10003	1851225	535027	50109	40212	10004	70221	10004	40008	10000	40100
50204	70145	50109	40109	10000	40106	10003	1851225	535027	50109	40212	10004	70221	10004	40008	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0105

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71253	50068	40063	10005	40156	10003	1851536	535356	50019	40032	10004	70041	10004	40004	10000	40010
50024	70105	50014	40014	10000	40010	10000	1850390	535101	50010	40020	10000	70020	10000	40004	10000	40010
50024	70105	50014	40014	10000	40010	10000	1850390	535101	50010	40020	10000	70020	10000	40004	10000	40010
50024	70105	50014	40014	10000	40010	10000	1850390	535101	50010	40020	10000	70020	10000	40004	10000	40010
50024	70105	50014	40014	10000	40010	10000	1850390	535101	50010	40020	10000	70020	10000	40004	10000	40010
50024	70189	50014	40014	10000	40010	10000	1850984	535299	50010	40020	10000	70020	10000	40004	10000	40010
50024	70105	50014	40014	10000	40010	10000	1850390	535101	50010	40020	10000	70020	10000	40004	10000	40010
50024	70105	50014	40014	10000	40010	10000	1850390	535101	50010	40020	10000	70112	10015	40017	10000	40010
50024	70107	50014	40014	10000	40010	10000	1850390	535101	50010	40020	10000	70020	10000	40004	10000	40010
50024	70105	50014	40014	10000	40010	10000	1850390	535101	50010	40020	10000	70020	10000	40004	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6, #8]!
  ldrb w0, [x7, #8]!
  ldrb w0, [x8, #8]!
  ldrb w0, [x9, #8]!
  ldrb w0, [x10, #8]!
  ldrb w0, [x11, #8]!
  ldrb w0, [x12, #8]!
  ldrb w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44477	160425	80312	80113	80315	80010	240642	642566	160122	80212	80012	80212	80012	80009	80000	80100
160204	43225	160109	80109	80000	80112	80011	240529	643473	160123	80212	80012	80253	80053	80050	80000	80100
160204	43243	160111	80110	80001	80113	80008	240702	634522	160116	80208	80008	80212	80012	80009	80000	80100
160204	43229	160109	80109	80000	80112	80009	240529	643666	160121	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80054	241098	620630	160208	80254	80054	80210	80010	80007	80000	80100
160204	43225	160109	80109	80000	80112	80011	240562	643477	160123	80212	80012	80212	80012	80009	80000	80100
160204	43226	160111	80109	80002	80112	80009	240523	643949	160119	80210	80010	80212	80012	80009	80000	80100
160204	43225	160109	80109	80000	80112	80011	240611	643266	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80010	240529	638781	160122	80212	80012	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80011	240529	645906	160123	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44459	160330	80221	80109	80224	80011	240340	642701	160033	80032	80012	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	645747	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	640103	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	642495	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	643028	160010	80020	80000	80073	80053	80050	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	641968	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	646574	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	646227	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	645260	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240304	643359	160010	80020	80000	80020	80000	80001	80000	80010

LDRB (pre-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations