Icestorm: EXTR (register, 32-bit) measurements

Code:

  extr w0, w0, w1, 13

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000
2004	1031	2001	2001	2000	7000	2000	2000	3000	2001	2000

Test 2: Latency 1->2

Code:

  extr w0, w0, w1, 13

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	10035	20110	20110	20113	70343	20113	20218	30227	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100
20204	10035	20110	20110	20113	70343	20113	20216	30224	20010	20100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0031

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	10057	20020	20020	20023	70073	20023	20038	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010
20024	10031	20011	20011	20010	70030	20010	20020	30020	20001	20010

Test 3: Latency 1->3

Code:

  extr w0, w1, w0, 13

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20106	379828	20105	20210	30215	20001	20100
20204	20030	20101	20101	20105	379979	20105	20212	30218	20001	20100
20204	20030	20101	20101	20105	379979	20105	20212	30218	20001	20100
20204	20030	20101	20101	20105	379979	20105	20212	30218	20001	20100
20204	20030	20101	20101	20105	379910	20105	20210	30218	20001	20100
20204	20030	20101	20101	20105	379979	20105	20212	30218	20001	20100
20204	20030	20101	20101	20105	379979	20105	20212	30218	20001	20100
20204	20030	20101	20101	20105	379979	20105	20212	30218	20001	20100
20204	20030	20101	20101	20105	379979	20105	20212	30218	20001	20100
20204	20030	20101	20101	20105	379979	20105	20212	30218	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20016	379685	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	379776	20010	20020	30020	20001	20010

Test 4: throughput

Count: 8

Code:

  extr w0, w8, w9, 13
  extr w1, w8, w9, 13
  extr w2, w8, w9, 13
  extr w3, w8, w9, 13
  extr w4, w8, w9, 13
  extr w5, w8, w9, 13
  extr w6, w8, w9, 13
  extr w7, w8, w9, 13

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	80046	160110	160110	160113	560343	160113	160218	240224	160010	160100
160204	80046	160110	160110	160113	560343	160113	160216	240224	160010	160100
160204	80035	160110	160110	160113	560343	160113	160216	240224	160010	160100
160204	80035	160110	160110	160113	560343	160113	160216	240224	160010	160100
160204	80035	160110	160110	160113	560343	160113	160216	240284	160040	160100
160204	80035	160110	160110	160113	560343	160113	160216	240224	160010	160100
160204	80035	160110	160110	160113	560343	160113	160216	240224	160010	160100
160205	80066	160140	160140	160150	560343	160113	160216	240224	160010	160100
160204	80035	160110	160110	160113	560343	160113	160216	240224	160010	160100
160204	80035	160110	160110	160113	560343	160113	160216	240224	160010	160100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	80057	160020	160020	160023	560030	160010	160020	240080	160031	160010
160024	80031	160011	160011	160010	560030	160010	160020	240020	160001	160010
160024	80031	160011	160011	160010	560030	160010	160020	240020	160001	160010
160024	80031	160011	160011	160010	560030	160010	160020	240083	160031	160010
160024	80031	160011	160011	160010	560030	160010	160020	240020	160001	160010
160024	80031	160011	160011	160010	560030	160010	160020	240020	160001	160010
160024	80031	160011	160011	160010	560030	160010	160020	240020	160001	160010
160024	80031	160011	160011	160010	560193	160060	160080	240020	160001	160010
160024	80031	160011	160011	160010	560030	160010	160020	240020	160001	160010
160024	80031	160011	160011	160010	560030	160010	160020	240020	160001	160010

EXTR (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations