Icestorm: ADCS (32-bit) measurements

Code:

  adcs w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	3000	1001	1000

Test 2: Latency 1->2

Code:

  adcs w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	251641	10106	10206	30218	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30344	10015	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253292	10028	10030	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30131	10032	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010

Test 3: Latency 1->3

Code:

  adcs w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10109	251774	10108	10208	30230	10001	10100
10204	10030	10101	10101	10106	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	30224	10001	10100
10204	10030	10101	10101	10108	251520	10106	10206	30224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253256	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	30020	10011	10010

Test 4: Latency 1->4

Chain cycles: 1

Code:

  adcs w0, w1, w2
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100
20204	20030	20201	20201	20208	509018	20208	20208	34409	2415	16821	1081	2	9529
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100
20204	20030	20201	20201	20208	509018	20208	20208	40216	0	20101	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20029	509854	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	510224	20069	20070	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010
20024	20030	20021	20021	20020	509904	20020	20020	40020	20011	10010

Test 5: Latency 4->2

Chain cycles: 1

Code:

  adcs w0, w1, w2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20030	20101	20101	20108	519234	20108	20216	40224	0	20001	0	20100
20204	20030	20101	20101	20107	519416	20107	20212	40232	0	20001	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	0	20001	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	0	20001	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	0	20001	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	0	20001	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	0	20001	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	0	20001	0	20100
20204	20030	20101	20101	20108	519548	20108	20216	40557	219	20117	54	20239
20204	20030	20101	20101	20108	519434	20107	20214	40232	0	20001	0	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	0	519507	0	0	20017	20032	0	0	40020	20001	20010
20025	20060	20025	20025	20058	9467	784150	126864	1064	46361	42671	11033	47	40052	20001	20010
20024	20030	20011	20011	20017	0	519852	0	0	20058	20083	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20019	0	519476	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519956	0	0	20058	20084	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010

Test 6: Latency 4->3

Chain cycles: 1

Code:

  adcs w0, w1, w2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519416	20107	20212	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40328	20015	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	40232	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	0	519507	0	0	20017	20032	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40052	20001	20010
20024	20030	20011	20011	20010	0	519598	0	0	20010	20020	0	0	40020	20001	20010

Test 7: Latency 4->4

Code:

  adcs w0, w1, w2

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10212	253108	10212	10214	30230	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10210	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	30224	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253167	10029	10032	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	30020	10011	10010

Test 8: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  adcs w0, w8, w9
  ands xzr, xzr, xzr
  adcs w1, w8, w9
  ands xzr, xzr, xzr
  adcs w2, w8, w9
  ands xzr, xzr, xzr
  adcs w3, w8, w9
  ands xzr, xzr, xzr
  adcs w4, w8, w9
  ands xzr, xzr, xzr
  adcs w5, w8, w9
  ands xzr, xzr, xzr
  adcs w6, w8, w9
  ands xzr, xzr, xzr
  adcs w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7992

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	64079	160114	160114	160120	0	682083	0	160118	160220	0	240230	160013	80100
160204	63937	160113	160113	160117	0	682516	0	160118	160220	0	240224	160011	80100
160204	63893	160111	160111	160118	0	681963	0	160116	160216	0	240224	160012	80100
160204	63938	160111	160111	160115	0	682256	0	160119	160220	0	240230	160015	80100
160204	63924	160111	160111	160118	0	682238	0	160115	160216	0	240224	160010	80100
160204	63939	160115	160115	160119	0	682205	0	160119	160220	0	240230	160015	80100
160204	63908	160111	160111	160115	0	682141	0	160115	160216	0	240284	160049	80100
160204	63892	160112	160112	160118	0	681993	0	160119	160220	0	240224	160011	80100
160204	63937	160113	160113	160119	0	682162	0	160115	160216	0	240230	160011	80100
160204	63922	160110	160110	160115	0	682170	0	160119	160220	0	240224	160010	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7985

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	65324	160023	160023	160028	681616	160026	160036	240020	160001	80010
160024	64061	160011	160011	160010	682544	160010	160020	240020	160001	80010
160024	63887	160011	160011	160010	682315	160010	160020	240020	160001	80010
160024	63881	160011	160011	160010	682619	160010	160020	240020	160001	80010
160024	63872	160011	160011	160010	682995	160068	160078	240020	160001	80010
160025	63838	160058	160058	160066	685949	160010	160020	240020	160001	80010
160024	63860	160011	160011	160010	682690	160010	160020	240020	160001	80010
160024	63881	160011	160011	160010	682598	160010	160020	240020	160001	80010
160024	63896	160011	160011	160010	682560	160010	160020	240020	160001	80010
160024	63878	160011	160011	160010	682570	160010	160020	240020	160001	80010

Test 9: throughput

Count: 4

Code:

  fcmp s0, s0
  adcs w0, w4, w5
  adcs w1, w4, w5
  adcs w2, w4, w5
  adcs w3, w4, w5

Initialization

  mov x4, 5
  mov x5, 6
  mov x6, 7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6208

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24830	50105	40103	10002	40111	10003	308693	40017	50116	40212	10004	120236	20008	40001	40100
50204	24840	50104	40101	10003	40112	10004	308503	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	120236	20008	40001	40100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6197

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24878	50016	40014	10002	40024	10004	313082	40013	50022	40029	10003	120020	20000	40001	40010
50024	24783	50011	40011	10000	40010	10000	311962	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311976	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010
50024	24789	50011	40011	10000	40010	10000	311978	40000	50010	40020	10000	120020	20000	40001	40010

Test 10: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  adcs w0, w7, w8
  adcs w1, w7, w8
  adcs w2, w7, w8
  adcs w3, w7, w8
  adcs w4, w7, w8
  adcs w5, w7, w8
  adcs w6, w7, w8

Initialization

  mov x7, 8
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5844

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	40921	80110	80110	80116	0	540886	0	0	80112	80212	0	0	210230	80007	70100
80204	40886	80106	80106	80112	0	541028	0	0	80112	80212	0	0	210230	80007	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	210230	80007	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	210230	80007	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	210230	80007	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	210230	80007	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	210230	80007	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	210344	80038	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	210230	80007	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	210230	80007	70100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5839

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	41031	80025	80025	80036	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40845	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010
80024	40876	80021	80021	80020	542624	80020	80020	210020	80011	70010

ADCS (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 4->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 9: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 10: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations