Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MSR (NZCV)

Test 1: uops

Code:

  msr nzcv, x0

Initialization

  mrs x0, nzcv

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	508	1001	1001	1000	3000	1000	1000	1000	1001
1004	399	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	393	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	393	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: throughput

Code:

  msr nzcv, x0

Initialization

  mrs x0, nzcv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 0.3714

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	3734	10114	10114	10119	30357	10119	10220	10220	10013	100
10204	3715	10113	10113	10118	30354	10118	10220	10216	10012	100
10204	3714	10113	10113	10118	30351	10117	10220	10220	10013	100
10204	3708	10113	10113	10118	30357	10119	10220	10220	10013	100
10204	3711	10113	10113	10118	30351	10117	10220	10220	10013	100
10204	3707	10112	10112	10116	30351	10117	10220	10220	10013	100
10204	3707	10112	10112	10116	30475	10157	10260	10220	10013	100
10204	3716	10113	10113	10118	30354	10118	10220	10220	10015	100
10204	3720	10115	10115	10119	30351	10117	10220	10220	10013	100
10204	3708	10112	10112	10117	30354	10118	10220	10220	10013	100

1000 unrolls and 10 iterations

Result (median cycles for code): 0.3659

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	3824	10033	10033	10038	30068	10020	10020	10020	10011	10
10024	3667	10021	10021	10020	30078	10020	10020	10020	10011	10
10024	3664	10021	10021	10020	30074	10020	10020	10020	10011	10
10024	3666	10021	10021	10020	30074	10020	10020	10020	10011	10
10024	3666	10021	10021	10020	30227	10057	10057	10020	10011	10
10024	3665	10021	10021	10020	30073	10020	10020	10020	10011	10
10024	3659	10021	10021	10020	30060	10020	10020	10020	10011	10
10024	3656	10021	10021	10020	30075	10020	10020	10020	10011	10
10024	3663	10021	10021	10020	30086	10020	10020	10020	10011	10
10024	3656	10021	10021	10020	30066	10020	10020	10020	10011	10