Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
casalh w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 4.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 74009 | 35217 | 3025 | 1 | 3024 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34560 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34398 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34447 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34397 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34432 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34400 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34396 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34396 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34383 | 3001 | 1 | 3000 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
Code:
casalh w0, w1, [x6] add x6, x6, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 9.0058
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 50208 | 90263 | 41834 | 11786 | 30048 | 11785 | 30003 | 42883 | 354976 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44267 | 14266 | 30001 | 14265 | 30003 | 42869 | 354998 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50205 | 90102 | 43740 | 13710 | 30030 | 13708 | 30003 | 42883 | 354969 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44267 | 14266 | 30001 | 14265 | 30003 | 42883 | 354966 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44267 | 14266 | 30001 | 14265 | 30003 | 42883 | 354971 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44267 | 14266 | 30001 | 14265 | 30003 | 42883 | 354969 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44267 | 14266 | 30001 | 14265 | 30003 | 42883 | 354965 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44267 | 14266 | 30001 | 14265 | 30003 | 42881 | 354965 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44267 | 14266 | 30001 | 14265 | 30036 | 38864 | 355241 | 0 | 42954 | 20223 | 30036 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44267 | 14266 | 30001 | 14265 | 30003 | 42881 | 354965 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14166 | 30000 | 0 | 20100 |
Result (median cycles for code): 9.0060
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 50028 | 90455 | 41745 | 11697 | 30048 | 11695 | 30003 | 42611 | 355239 | 0 | 44178 | 20021 | 30003 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90058 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 355217 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 30000 | 14175 | 30000 | 42614 | 355216 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 30000 | 14175 | 30000 | 42609 | 355186 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90052 | 44176 | 14176 | 30000 | 14175 | 30000 | 42610 | 355235 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 355209 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 30000 | 14175 | 30000 | 42611 | 355211 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 30000 | 14175 | 30000 | 42611 | 355204 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 30000 | 14175 | 30000 | 42611 | 355213 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 30000 | 14175 | 30000 | 42610 | 355228 | 0 | 44175 | 20020 | 30000 | 0 | 20020 | 60000 | 14166 | 30000 | 20010 |
Code:
casalh w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 24.0046
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 40207 | 240149 | 33469 | 3434 | 30035 | 1771 | 30003 | 920646 | 2938435 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8323 | 30000 | 0 | 10100 |
| 40205 | 240075 | 36628 | 6598 | 30030 | 3364 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240046 | 38398 | 8397 | 30001 | 4265 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40206 | 240074 | 35312 | 5269 | 30043 | 2694 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10214 | 60072 | 0 | 4769 | 30000 | 0 | 10100 |
| 40204 | 240046 | 38398 | 8397 | 30001 | 4265 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240046 | 38398 | 8397 | 30001 | 4265 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240046 | 38398 | 8397 | 30001 | 4265 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240046 | 38398 | 8397 | 30001 | 4265 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240046 | 38398 | 8397 | 30001 | 4265 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10212 | 60072 | 0 | 6221 | 30000 | 0 | 10100 |
| 40205 | 240097 | 33891 | 3861 | 30030 | 1985 | 30003 | 920658 | 2938481 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
Result (median cycles for code): 24.0046
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 40027 | 240157 | 33385 | 3345 | 30040 | 1681 | 30003 | 920388 | 2938571 | 34178 | 10021 | 30003 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920401 | 2938594 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30036 | 499800 | 2938829 | 32311 | 10032 | 30036 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938556 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10032 | 60072 | 5959 | 30000 | 10010 |